drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programming

The PHY_C20_VDR_HDMI_RATE registers 7:2 bits are reserved and they are
not specified as a must-be-zero field. Accordingly this reserved field
shouldn't be zeroed; to ensure that use an RMW to update the
PHY_C20_HDMI_RATE field (which is bits 1:0 of the register).

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20251015125446.3931198-7-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6e49659d2f170be305a08131f56ecdbf335265ad..f8c1338f90539232ae7187bdfc969efa43c7cd3f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2714,9 +2714,10 @@ static void intel_c20_pll_program(struct intel_display *display,
                      MB_WRITE_COMMITTED);
 
        if (!is_dp)
-               intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
-                               intel_c20_get_hdmi_rate(port_clock),
-                               MB_WRITE_COMMITTED);
+               intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
+                             PHY_C20_HDMI_RATE_MASK,
+                             intel_c20_get_hdmi_rate(port_clock),
+                             MB_WRITE_COMMITTED);
 
        /*
         * 7. Write Vendor specific registers to toggle context setting to load

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 0743a3e2d15f91a3333b38f7eeaf7be3b975353b..86e2e1c7babfb8bceb38509de1c164676c6d3d19 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -304,6 +304,8 @@
 #define   PHY_C20_DP_RATE(val)         REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
 #define   PHY_C20_CONTEXT_TOGGLE       REG_BIT8(0)
 #define PHY_C20_VDR_HDMI_RATE          0xD01
+#define   PHY_C20_HDMI_RATE_MASK       REG_GENMASK8(1, 0)
+#define   PHY_C20_HDMI_RATE(val)       REG_FIELD_PREP8(PHY_C20_HDMI_RATE_MASK, val)
 #define PHY_C20_VDR_CUSTOM_WIDTH       0xD02
 #define   PHY_C20_CUSTOM_WIDTH_MASK    REG_GENMASK(1, 0)
 #define   PHY_C20_CUSTOM_WIDTH(val)    REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)