]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: ti: k3-am64: Enable remote processors at board level
authorBeleswar Padhi <b-padhi@ti.com>
Mon, 8 Sep 2025 14:28:00 +0000 (19:58 +0530)
committerNishanth Menon <nm@ti.com>
Fri, 12 Sep 2025 04:15:30 +0000 (09:45 +0530)
Remote Processors defined in top-level AM64x SoC dtsi files are
incomplete without the memory carveouts and mailbox assignments which
are only known at board integration level.

Therefore, disable the remote processors at SoC level and enable them at
board level where above information is available.

Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de> # phycore-am64x
Tested-by: Hari Nagalla <hnagalla@ti.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Andrew Davis <afd@ti.com>
Link: https://patch.msgid.link/20250908142826.1828676-9-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
arch/arm64/boot/dts/ti/k3-am64-main.dtsi
arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
arch/arm64/boot/dts/ti/k3-am642-evm.dts
arch/arm64/boot/dts/ti/k3-am642-sk.dts
arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi

index c7e5da37486ae2c535c42d55da65aa2fb67dba78..d872cc671094f1467f7ce62fe22350e91b83f938 100644 (file)
                         <0x78200000 0x00 0x78200000 0x08000>,
                         <0x78300000 0x00 0x78300000 0x08000>;
                power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
 
                main_r5fss0_core0: r5f@78000000 {
                        compatible = "ti,am64-r5f";
                        ti,atcm-enable = <1>;
                        ti,btcm-enable = <1>;
                        ti,loczrama = <1>;
+                       status = "disabled";
                };
 
                main_r5fss0_core1: r5f@78200000 {
                        ti,atcm-enable = <1>;
                        ti,btcm-enable = <1>;
                        ti,loczrama = <1>;
+                       status = "disabled";
                };
        };
 
                         <0x78600000 0x00 0x78600000 0x08000>,
                         <0x78700000 0x00 0x78700000 0x08000>;
                power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+               status = "disabled";
 
                main_r5fss1_core0: r5f@78400000 {
                        compatible = "ti,am64-r5f";
                        ti,atcm-enable = <1>;
                        ti,btcm-enable = <1>;
                        ti,loczrama = <1>;
+                       status = "disabled";
                };
 
                main_r5fss1_core1: r5f@78600000 {
                        ti,atcm-enable = <1>;
                        ti,btcm-enable = <1>;
                        ti,loczrama = <1>;
+                       status = "disabled";
                };
        };
 
index d9d491b12c33a869f0dc8848c68fd58f79761f67..03c46d74ebb5ddbb9a0d54a678dfe97b4a47cf93 100644 (file)
        bootph-all;
 };
 
+&main_r5fss0 {
+       status = "okay";
+};
+
 &main_r5fss0_core0 {
        mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
        memory-region = <&main_r5fss0_core0_dma_memory_region>,
                        <&main_r5fss0_core0_memory_region>;
+       status = "okay";
 };
 
 &main_r5fss0_core1 {
        mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
        memory-region = <&main_r5fss0_core1_dma_memory_region>,
                        <&main_r5fss0_core1_memory_region>;
+       status = "okay";
+};
+
+&main_r5fss1 {
+       status = "okay";
 };
 
 &main_r5fss1_core0 {
        mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
        memory-region = <&main_r5fss1_core0_dma_memory_region>,
                        <&main_r5fss1_core0_memory_region>;
+       status = "okay";
 };
 
 &main_r5fss1_core1 {
        mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
        memory-region = <&main_r5fss1_core1_dma_memory_region>,
                        <&main_r5fss1_core1_memory_region>;
+       status = "okay";
 };
 
 &mcu_m4fss {
index e01866372293babcbe6687f32a094e9daaa815ec..a07503b192c92e3a76f52bb20664913c7eb97cc4 100644 (file)
        };
 };
 
+&main_r5fss0 {
+       status = "okay";
+};
+
 &main_r5fss0_core0 {
        mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
        memory-region = <&main_r5fss0_core0_dma_memory_region>,
                        <&main_r5fss0_core0_memory_region>;
+       status = "okay";
 };
 
 &main_r5fss0_core1 {
        mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
        memory-region = <&main_r5fss0_core1_dma_memory_region>,
                        <&main_r5fss0_core1_memory_region>;
+       status = "okay";
+};
+
+&main_r5fss1 {
+       status = "okay";
 };
 
 &main_r5fss1_core0 {
        mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
        memory-region = <&main_r5fss1_core0_dma_memory_region>,
                        <&main_r5fss1_core0_memory_region>;
+       status = "okay";
 };
 
 &main_r5fss1_core1 {
        mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
        memory-region = <&main_r5fss1_core1_dma_memory_region>,
                        <&main_r5fss1_core1_memory_region>;
+       status = "okay";
 };
 
 &mcu_m4fss {
index 1deaa0be0085c4e64136d3e8f68fdcd62ca7e068..ae4a6552644c3dbd78c11fa7559f146d3aaf89ec 100644 (file)
        };
 };
 
+&main_r5fss0 {
+       status = "okay";
+};
+
 &main_r5fss0_core0 {
        mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
        memory-region = <&main_r5fss0_core0_dma_memory_region>,
                        <&main_r5fss0_core0_memory_region>;
+       status = "okay";
 };
 
 &main_r5fss0_core1 {
        mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
        memory-region = <&main_r5fss0_core1_dma_memory_region>,
                        <&main_r5fss0_core1_memory_region>;
+       status = "okay";
+};
+
+&main_r5fss1 {
+       status = "okay";
 };
 
 &main_r5fss1_core0 {
        mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
        memory-region = <&main_r5fss1_core0_dma_memory_region>,
                        <&main_r5fss1_core0_memory_region>;
+       status = "okay";
 };
 
 &main_r5fss1_core1 {
        mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
        memory-region = <&main_r5fss1_core1_dma_memory_region>,
                        <&main_r5fss1_core1_memory_region>;
+       status = "okay";
 };
 
 &mcu_m4fss {
index a5cec9a075109aeec335e3f4d22a9fd60a3cd813..d0c1e4dc1da7fe3058a333d8746b0c061da4eb91 100644 (file)
        };
 };
 
+&main_r5fss0 {
+       status = "okay";
+};
+
 &main_r5fss0_core0 {
        mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
        memory-region = <&main_r5fss0_core0_dma_memory_region>,
                        <&main_r5fss0_core0_memory_region>;
+       status = "okay";
 };
 
 &main_r5fss0_core1 {
        mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
        memory-region = <&main_r5fss0_core1_dma_memory_region>,
                        <&main_r5fss0_core1_memory_region>;
+       status = "okay";
+};
+
+&main_r5fss1 {
+       status = "okay";
 };
 
 &main_r5fss1_core0 {
        mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
        memory-region = <&main_r5fss1_core0_dma_memory_region>,
                        <&main_r5fss1_core0_memory_region>;
+       status = "okay";
 };
 
 &main_r5fss1_core1 {
        mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
        memory-region = <&main_r5fss1_core1_dma_memory_region>,
                        <&main_r5fss1_core1_memory_region>;
+       status = "okay";
 };
 
 /* SoC default UART console */
index 828d815d6bdfc24d96c9e36f16643ed8bb59abfb..876cbb21961d03d5e3c436a65c3ba8f6fa5d065f 100644 (file)
        };
 };
 
+&main_r5fss0 {
+       status = "okay";
+};
+
 &main_r5fss0_core0 {
        mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
        memory-region = <&main_r5fss0_core0_dma_memory_region>,
                        <&main_r5fss0_core0_memory_region>;
+       status = "okay";
 };
 
 &main_r5fss0_core1 {
        mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
        memory-region = <&main_r5fss0_core1_dma_memory_region>,
                        <&main_r5fss0_core1_memory_region>;
+       status = "okay";
+};
+
+&main_r5fss1 {
+       status = "okay";
 };
 
 &main_r5fss1_core0 {
        mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
        memory-region = <&main_r5fss1_core0_dma_memory_region>,
                        <&main_r5fss1_core0_memory_region>;
+       status = "okay";
 };
 
 &main_r5fss1_core1 {
        mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
        memory-region = <&main_r5fss1_core1_dma_memory_region>,
                        <&main_r5fss1_core1_memory_region>;
+       status = "okay";
 };
 
 &ospi0 {