match.pd: Add missing type check to reduc(ctor) pattern [PR121772]

This is a cherry-pick of a7a9b7badc0ba95b510c7e61da6439fca78e31d3
together with a follow-up fix to the test
(0c670d38455c788ac0447e3b86ba621521d44bce) squashed into it.

In this PR we have a reduction of a vector constructor, where the
type of the constructor is int16x8_t and the elements are int16x4_t;
i.e. it is representing a concatenation of two vectors.

This triggers a match.pd pattern which looks like it was written to
handle reductions of vector constructors where the elements of the ctor
are scalars, not vectors.  There is no type check to enforce this
property, which leads to the pattern replacing a reduction to scalar
with an int16x4_t vector in this case, which of course is a type error,
leading to an invalid GIMPLE ICE.

This patch adds a type check to the pattern, only going ahead with the
transformation if the element type of the ctor matches that of the
reduction.

gcc/ChangeLog:

	PR tree-optimization/121772
	* match.pd: Add type check to reduc(ctor) pattern.

gcc/testsuite/ChangeLog:

	PR tree-optimization/121772
	* gcc.target/aarch64/torture/pr121772.c: New test.

(cherry picked from commit a7a9b7badc0ba95b510c7e61da6439fca78e31d3)

diff --git a/gcc/match.pd b/gcc/match.pd
index 88f2e37a2b8996f76c209662ff3eb6c53698bc31..d3af36f8de3ed65a9c932a5cb602c3211c297213 100644 (file)
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -8121,6 +8121,7 @@ and,
                         ? gimple_assign_rhs1 (SSA_NAME_DEF_STMT (@0)) : @0);
            tree elt = ctor_single_nonzero_element (ctor); }
       (if (elt
+          && types_match (type, TREE_TYPE (elt))
           && !HONOR_SNANS (type)
           && !HONOR_SIGNED_ZEROS (type))
        { elt; }))))

diff --git a/gcc/testsuite/gcc.target/aarch64/torture/pr121772.c b/gcc/testsuite/gcc.target/aarch64/torture/pr121772.c
new file mode 100644 (file)
index 0000000..d47a026
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/torture/pr121772.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-fchecking" } */
+#include <arm_neon.h>
+int16_t f(int16x4_t b) {
+  return vaddvq_s16(vcombine_s16(b, vdup_n_s16 (0)));
+}