ARM: tegra: Add DFLL clock support for Tegra114

Add DFLL clock node to common Tegra114 device tree along with clocks
property to cpu node.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
index 4caf2073c5561e8508afb5c2e87f2cbfec7f963c..a2a50f959927ddfe3461135a8337cd51f6b68747 100644 (file)
--- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/memory/tegra114-mc.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/nvidia,tegra114-car.h>
 #include <dt-bindings/soc/tegra-pmc.h>
 
 / {
@@ -693,6 +694,29 @@
                #nvidia,mipi-calibrate-cells = <1>;
        };
 
+       dfll: clock@70110000 {
+               compatible = "nvidia,tegra114-dfll";
+               reg = <0x70110000 0x100>, /* DFLL control */
+                     <0x70110000 0x100>, /* I2C output control */
+                     <0x70110100 0x100>, /* Integrated I2C controller */
+                     <0x70110200 0x100>; /* Look-up table RAM */
+               interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>,
+                        <&tegra_car TEGRA114_CLK_DFLL_REF>,
+                        <&tegra_car TEGRA114_CLK_I2C5>;
+               clock-names = "soc", "ref", "i2c";
+               resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>;
+               reset-names = "dvco";
+               #clock-cells = <0>;
+               clock-output-names = "dfllCPU_out";
+               nvidia,droop-ctrl = <0x00000f00>;
+               nvidia,force-mode = <1>;
+               nvidia,cf = <10>;
+               nvidia,ci = <0>;
+               nvidia,cg = <2>;
+               status = "disabled";
+       };
+
        mmc@78000000 {
                compatible = "nvidia,tegra114-sdhci";
                reg = <0x78000000 0x200>;
@@ -824,6 +848,15 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a15";
                        reg = <0>;
+
+                       clocks = <&tegra_car TEGRA114_CLK_CCLK_G>,
+                                <&tegra_car TEGRA114_CLK_CCLK_LP>,
+                                <&tegra_car TEGRA114_CLK_PLL_X>,
+                                <&tegra_car TEGRA114_CLK_PLL_P>,
+                                <&dfll>;
+                       clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
+                       /* FIXME: what's the actual transition time? */
+                       clock-latency = <300000>;
                };
 
                cpu1: cpu@1 {