drm/amdgpu: Enable MES lr_compute_wa by default

commit 1fb710793ce2619223adffaf981b1ff13cd48f17 upstream.

The MES set resources packet has an optional bit 'lr_compute_wa'
which can be used for preventing MES hangs on long compute jobs.

Set this bit by default.

Co-developed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 3f6a828cad8ad809f712e40165f13abe7ed3ba0c..1445da1f53afb48276706c29d8e42b69578e947e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -711,6 +711,12 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
        mes_set_hw_res_pkt.enable_reg_active_poll = 1;
        mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
        mes_set_hw_res_pkt.oversubscription_timer = 50;
+       if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x7f)
+               mes_set_hw_res_pkt.enable_lr_compute_wa = 1;
+       else
+               dev_info_once(mes->adev->dev,
+                             "MES FW version must be >= 0x7f to enable LR compute workaround.\n");
+
        if (amdgpu_mes_log_enable) {
                mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
                mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr =

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index 6b222630f3fa1d3b047122254f46bc31c06a3f3d..39caac14d5fe1c5e2471aa8b12817b84dc9f91b0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -738,6 +738,11 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
        mes_set_hw_res_pkt.use_different_vmid_compute = 1;
        mes_set_hw_res_pkt.enable_reg_active_poll = 1;
        mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
+       if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x82)
+               mes_set_hw_res_pkt.enable_lr_compute_wa = 1;
+       else
+               dev_info_once(adev->dev,
+                             "MES FW version must be >= 0x82 to enable LR compute workaround.\n");
 
        /*
         * Keep oversubscribe timer for sdma . When we have unmapped doorbell

diff --git a/drivers/gpu/drm/amd/include/mes_v11_api_def.h b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
index 15680c3f49704eb591803a6af8baf51f2800dc26..ab1cfc92dbeb1b2a3d9798b1fd68ad8ec17946a4 100644 (file)
--- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h
+++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
@@ -238,7 +238,8 @@ union MESAPI_SET_HW_RESOURCES {
                                uint32_t enable_mes_sch_stb_log : 1;
                                uint32_t limit_single_process : 1;
                                uint32_t is_strix_tmz_wa_enabled  :1;
-                               uint32_t reserved : 13;
+                               uint32_t enable_lr_compute_wa : 1;
+                               uint32_t reserved : 12;
                        };
                        uint32_t        uint32_t_all;
                };

diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
index d85ffab2aff9de3e268c0ed5c9174a62adc2242f..a402974939d63c49899842a644b6ea5fc2bcbd72 100644 (file)
--- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
+++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
@@ -286,7 +286,8 @@ union MESAPI_SET_HW_RESOURCES {
                                uint32_t limit_single_process : 1;
                                uint32_t unmapped_doorbell_handling: 2;
                                uint32_t enable_mes_fence_int: 1;
-                               uint32_t reserved : 10;
+                               uint32_t enable_lr_compute_wa : 1;
+                               uint32_t reserved : 9;
                        };
                        uint32_t uint32_all;
                };