realtek: add support for Zyxel XMG1915-10E

The XMG1915-10E is a switch with 8 copper ports and 2 SFP+ cages.

Specifications:
---------------
  * SoC: RTL9302C
  * Flash: 32 MiB SPI NOR flash
  * RAM: 256 MiB
  * Ethernet: 8x 10/100/1000/2500 Mbps (RTL8224)
  * SFP: 2x SFP+ cages
  * UART: 1x 4 pins serial header, 115200 bauds, 8n1, 3.3v logic levels,
          pinout: unused (top), TX, RX, GND (bottom)
  * Buttons: 1x "Reset" button

Works:
------
  - 2 SFP+ cages either 1G/10G or 2.5G
  - 8*2.5G Ethernet ports
  - Switch function
  - LEDs
  - Boot from flash
  - Assigning MAC addresses from flash

Ethernet ports:
---------------
The 8x 2.5Gbps ethernet ports are provided by two RTL8224 chips. The
ports are supported by the upstream realtek PHY driver plus a local
initialization patch for the 10g-qxgmii mode.

Installation:
-------------
This device uses ZyNOS instead of Linux which makes the installation a
bit cumbersome. OpenWRT will be installed on the slot of the second
firmware image, thus the switch original firmware can be booted with a
little change. The serial console is required.

1. Set the switch to boot from the first image. This is required to
   be sure not to be blocked in the middle of the installation
   procedure.

2. Connect to the switch using the serial adapter and interrupt the boot
   process by pressing "Enter" repeatedly.

3. Load the OpenWRT initramfs image using xmodem. From bootext console
   (use ATHE to get the list of commands):

   > ATUP 81800000,file_length
   > ATGO 81800000

4. Wait for OpenWRT to boot, once this is done transfer the loader
   binary and the sysupgrade image to /tmp using scp.

5. Install OpenWRT permanently by writing the images on the flash:

  > mtd write /tmp/loader.bin loader
  > mtd write /tmp/sysupgrade.bin firmware

6. Reboot the switch and from the stock firmware set the configuration
   to boot from the second image (Maintenance > Firmware upgrade > Boot
   image).

7. Reboot again and enjoy OpenWRT.

Recovery/Return to stock:
-------------------------
1. Connect the switch using the serial adapter and interrupt the boot
   process during the "DRAM POST: Testing:" sequence by pressing '$'
   until the "XMG1915$" prompt appears.

2. Start an ymodem upgrade using the following command and use an xmodem
   upload tool to send the .bin file provided in an OEM upgrade package.

   XMG1915$ upgradeY image2 81000000 115200
   ## Ready for binary (ymodem) download to 0x081000000 at 115200 bps...

3. Wait for the upgrade process to finish and reboot the switch.

Signed-off-by: Damien Dejean <dam.dejean@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21341
Signed-off-by: Robert Marko <robimarko@gmail.com>

diff --git a/target/linux/realtek/dts/rtl9302_zyxel_xmg1915-10e.dts b/target/linux/realtek/dts/rtl9302_zyxel_xmg1915-10e.dts
new file mode 100644 (file)
index 0000000..25a73e1
--- /dev/null
+++ b/target/linux/realtek/dts/rtl9302_zyxel_xmg1915-10e.dts
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/dts-v1/;
+
+#include "macros.dtsi"
+#include "rtl930x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+       compatible = "zyxel,xmg1915-10e", "realtek,rtl9302c-soc";
+       model = "Zyxel XMG1915-10E Switch";
+
+       aliases {
+               label-mac-device = &ethernet0;
+               led-boot = &led_pwr_sys_green;
+               led-failsafe = &led_pwr_sys_red;
+               led-running = &led_pwr_sys_green;
+               led-upgrade = &led_pwr_sys_green;
+       };
+
+       leds {
+               compatible = "gpio-leds";
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinmux_disable_sys_led>;
+
+               led_pwr_sys_green: led-0 {
+                       color = <LED_COLOR_ID_GREEN>;
+                       function = LED_FUNCTION_POWER;
+                       gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+                       default-state = "on";
+               };
+
+               led_pwr_sys_red: led-1 {
+                       color = <LED_COLOR_ID_RED>;
+                       function = LED_FUNCTION_POWER;
+                       gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+                       default-state = "off";
+               };
+       };
+
+       led_set: led_set {
+               compatible = "realtek,rtl9300-leds";
+               active-low;
+
+               /* Copper */
+               led_set0 = <(RTL93XX_LED_SET_100M | RTL93XX_LED_SET_LINK |
+                            RTL93XX_LED_SET_ACT)
+                           (RTL93XX_LED_SET_100M |RTL93XX_LED_SET_1G |
+                            RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK |
+                            RTL93XX_LED_SET_ACT)
+                           (RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK |
+                            RTL93XX_LED_SET_ACT)>;
+               /* SFP+ */
+               led_set1 = <(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_2P5G |
+                            RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
+                            (RTL93XX_LED_SET_10G | RTL93XX_LED_SET_2P5G |
+                            RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
+
+               /* PoE and Cloud are 4 leds in total but software managed.
+                  Assign them to led_set 1 to avoid shifting the others
+                  incorrectly. */
+               realtek,led-set1-force-port-mask = <0x01800000>;
+       };
+
+       keys {
+               compatible = "gpio-keys";
+
+               mode {
+                       label = "restore";
+                       gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+                       linux,code = <BTN_0>;
+               };
+       };
+
+       sfp0: sfp-p9 {
+               compatible = "sff,sfp";
+               i2c-bus = <&i2c0>;
+               mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
+               los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+               tx-fault-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+               tx-disable-gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+       };
+
+       sfp1: sfp-p10 {
+               compatible = "sff,sfp";
+               i2c-bus = <&i2c1>;
+               mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
+               los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+               tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+               tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+       };
+};
+
+&i2c_mst1 {
+       status = "okay";
+
+       /* i2c of the left SFP+ cage seen from the front; port 9 */
+       i2c0: i2c@0 {
+               reg = <0>;
+       };
+
+       /* i2c of the right SFP+ cage seen from the front; port 10 */
+       i2c1: i2c@1 {
+               reg = <1>;
+       };
+};
+
+&spi0 {
+       status = "okay";
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <10000000>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "bootbase";
+                               reg = <0x0 0x80000>;
+                               read-only;
+
+                               compatible = "fixed-partitions";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+
+                               partition@0 {
+                                       label = "u-boot";
+                                       reg = <0x0 0x7e000>;
+                               };
+
+                               partition@7e000 {
+                                       label = "u-boot-env2";
+                                       reg = <0x7e000 0x1000>;
+                               };
+
+                               partition@7f000 {
+                                       label = "mrd";
+                                       reg = <0x7f000 0x1000>;
+
+                                       nvmem-layout {
+                                               compatible = "fixed-layout";
+                                               #address-cells = <1>;
+                                               #size-cells = <1>;
+
+                                               /* 12 addresses are available */
+                                               macaddr_factory: macaddr@ff8 {
+                                                       compatible = "mac-base";
+                                                       reg = <0xff8 0x6>;
+                                                       #nvmem-cell-cells = <1>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       partition@80000 {
+                               label = "reserved";
+                               reg = <0x80000 0xf80000>;
+                               read-only;
+                       };
+
+                       partition@1260000 {
+                               label = "loader";
+                               reg = <0x1260000 0x30000>;
+                       };
+
+                       partition@1290000 {
+                               label = "firmware";
+                               reg = <0x1290000 0xd70000>;
+                               compatible = "openwrt,uimage", "denx,uimage";
+                       };
+               };
+       };
+};
+
+&mdio_bus0 {
+       /* External RTL8224 PHY */
+       phy0: ethernet-phy@0 {
+               reg = <0>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+               enet-phy-pair-order = <0>;
+               enet-phy-pair-polarity = <0>;
+       };
+       phy1: ethernet-phy@1 {
+               reg = <1>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+               enet-phy-pair-order = <0>;
+               enet-phy-pair-polarity = <0>;
+       };
+       phy2: ethernet-phy@2 {
+               reg = <2>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+               enet-phy-pair-order = <1>;
+               enet-phy-pair-polarity = <0>;
+       };
+       phy3: ethernet-phy@3 {
+               reg = <3>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+               enet-phy-pair-order = <1>;
+               enet-phy-pair-polarity = <0>;
+       };
+};
+
+&mdio_bus1 {
+       /* External RTL8224 PHY */
+       phy8: ethernet-phy@4 {
+               reg = <4>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+               enet-phy-pair-order = <0>;
+               enet-phy-pair-polarity = <0>;
+       };
+       phy9: ethernet-phy@5 {
+               reg = <5>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+               enet-phy-pair-order = <0>;
+               enet-phy-pair-polarity = <0>;
+       };
+       phy10: ethernet-phy@6 {
+               reg = <6>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+               enet-phy-pair-order = <1>;
+               enet-phy-pair-polarity = <0>;
+       };
+       phy11: ethernet-phy@7 {
+               reg = <7>;
+               compatible = "ethernet-phy-ieee802.3-c45";
+               enet-phy-pair-order = <1>;
+               enet-phy-pair-polarity = <0>;
+       };
+};
+
+&ethernet0 {
+       nvmem-cells = <&macaddr_factory 0>;
+       nvmem-cell-names = "mac-address";
+};
+
+&switch0 {
+       ethernet-ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               /* Copper ports */
+               SWITCH_PORT_LED(0, 1, 2, 0, 10g-qxgmii)
+               SWITCH_PORT_LED(1, 2, 2, 0, 10g-qxgmii)
+               SWITCH_PORT_LED(2, 3, 2, 0, 10g-qxgmii)
+               SWITCH_PORT_LED(3, 4, 2, 0, 10g-qxgmii)
+               SWITCH_PORT_LED(8, 5, 3, 0, 10g-qxgmii)
+               SWITCH_PORT_LED(9, 6, 3, 0, 10g-qxgmii)
+               SWITCH_PORT_LED(10, 7, 3, 0, 10g-qxgmii)
+               SWITCH_PORT_LED(11, 8, 3, 0, 10g-qxgmii)
+
+               /* SFP cages */
+               SWITCH_PORT_SFP(25, 9, 7, 1, 0)
+               SWITCH_PORT_SFP(27, 10, 9, 1, 1)
+
+               port@28 {
+                       ethernet = <&ethernet0>;
+                       reg = <28>;
+                       phy-mode = "internal";
+                       fixed-link {
+                               speed = <1000>;
+                               full-duplex;
+                       };
+               };
+       };
+};

diff --git a/target/linux/realtek/image/rtl930x.mk b/target/linux/realtek/image/rtl930x.mk
index f1cf43dc5fb0d11d1bc42b98f15d70be5feeb639..8731e4ba612cfad8b22dd715d7a399eff8f42a34 100644 (file)
--- a/target/linux/realtek/image/rtl930x.mk
+++ b/target/linux/realtek/image/rtl930x.mk
@@ -216,3 +216,20 @@ define Device/zyxel_xgs1250-12-b1
   DEVICE_VARIANT := B1
 endef
 TARGET_DEVICES += zyxel_xgs1250-12-b1
+
+define Device/zyxel_xmg1915-10e
+  SOC := rtl9302
+  ZYXEL_VERS := ABWE
+  DEVICE_VENDOR := Zyxel
+  DEVICE_MODEL := XMG1915-10E
+  FLASH_ADDR := 0xb5290000
+ifeq ($(IB),)
+  ARTIFACTS := loader.bin
+  ARTIFACT/loader.bin := \
+    rt-loader-standalone | \
+    zynsig
+endif
+  $(Device/rt-loader-bootbase)
+  IMAGE_SIZE := 13760k
+endef
+TARGET_DEVICES += zyxel_xmg1915-10e