arm64: dts: qcom: lemans-evk: Enable PCIe support

Enable PCIe0 and PCIe1 along with the respective phy-nodes.

PCIe0 is routed to an m.2 E key connector on the mainboard for wifi
attaches while PCIe1 routes to a standard PCIe x4 expansion slot.

Signed-off-by: Sushrut Shree Trivedi <quic_sushruts@quicinc.com>
Signed-off-by: Wasim Nazir <wasim.nazir@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250916-lemans-evk-bu-v5-5-53d7d206669d@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts
index 97428d9e3e41a63ee719e1e94b1dcecea7bfd2c6..99400ff12cfdcec00e19bceb69afa1ebc130300b 100644 (file)
--- a/arch/arm64/boot/dts/qcom/lemans-evk.dts
+++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts
@@ -431,6 +431,40 @@
        status = "okay";
 };
 
+&pcie0 {
+       perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+
+       pinctrl-0 = <&pcie0_default_state>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&pcie0_phy {
+       vdda-phy-supply = <&vreg_l5a>;
+       vdda-pll-supply = <&vreg_l1c>;
+
+       status = "okay";
+};
+
+&pcie1 {
+       perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
+
+       pinctrl-0 = <&pcie1_default_state>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&pcie1_phy {
+       vdda-phy-supply = <&vreg_l5a>;
+       vdda-pll-supply = <&vreg_l1c>;
+
+       status = "okay";
+};
+
 &qupv3_id_0 {
        status = "okay";
 };
@@ -447,6 +481,54 @@
        clock-frequency = <32768>;
 };
 
+&tlmm {
+       pcie0_default_state: pcie0-default-state {
+               clkreq-pins {
+                       pins = "gpio1";
+                       function = "pcie0_clkreq";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               perst-pins {
+                       pins = "gpio2";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               wake-pins {
+                       pins = "gpio0";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+
+       pcie1_default_state: pcie1-default-state {
+               clkreq-pins {
+                       pins = "gpio3";
+                       function = "pcie1_clkreq";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               perst-pins {
+                       pins = "gpio4";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               wake-pins {
+                       pins = "gpio5";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+};
+
 &uart10 {
        compatible = "qcom,geni-debug-uart";
        pinctrl-0 = <&qup_uart10_default>;