arm64: tegra: Add MISC registers on Tegra186

The MISC register block found on Tegra186 SoCs contains registers that
can be used to identify a given chip and various strapping options.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 46d1f287fb0fe0df9d66339c41d3d9f2ebbca9e4..11795dbd30f0720f6cca6149cf6adde1762c52f9 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -13,6 +13,12 @@
        #address-cells = <2>;
        #size-cells = <2>;
 
+       misc@100000 {
+               compatible = "nvidia,tegra186-misc";
+               reg = <0x0 0x00100000 0x0 0xf000>,
+                     <0x0 0x0010f000 0x0 0x1000>;
+       };
+
        gpio: gpio@2200000 {
                compatible = "nvidia,tegra186-gpio";
                reg-names = "security", "gpio";