[AArch64] vqneg and vqabs intrinsics implementation.

This patch implements vqneg_s64, vqnegd_s64, vqabs_s64 and vqabsd_s64
AArch64 intrinsics.

From-SVN: r209640

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eeaa5e44146eaf9416b30d86ca8f206884e1022e..23d05eeb8a39f3cc08d423eaa936d4997ab8f785 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>
+
+       * gcc/config/aarch64/aarch64-simd.md (aarch64_s<optab><mode>):
+       Pattern extended.
+       * config/aarch64/aarch64-simd-builtins.def (sqneg): Iterator
+       extended.
+       (sqabs): Likewise.
+       * config/aarch64/arm_neon.h (vqneg_s64): New intrinsic.
+       (vqnegd_s64): Likewise.
+       (vqabs_s64): Likewise.
+       (vqabsd_s64): Likewise.
+
 2014-04-22  Richard Henderson  <rth@redhat.com>
 
        * config/sparc/sparc.c (sparc_init_modes): Hoist GET_MODE_SIZE

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index c5e3b3e9fb3f3ba95ab6066e518d10c6b78c4ecf..d4c7403748d00ade9a602fa4ed2bf74e950ce9d5 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -142,8 +142,8 @@
   BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
   BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
   /* Implemented by aarch64_s<optab><mode>.  */
-  BUILTIN_VSDQ_I_BHSI (UNOP, sqabs, 0)
-  BUILTIN_VSDQ_I_BHSI (UNOP, sqneg, 0)
+  BUILTIN_VSDQ_I (UNOP, sqabs, 0)
+  BUILTIN_VSDQ_I (UNOP, sqneg, 0)
 
   BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane, 0)
   BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane, 0)

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 995b4a81acd0838347965e629147d322f7351fa7..753ca1c9e9e65ea5dcec0a3b220117f04269f842 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -2610,9 +2610,9 @@
 ;; <su>q<absneg>
 
 (define_insn "aarch64_s<optab><mode>"
-  [(set (match_operand:VSDQ_I_BHSI 0 "register_operand" "=w")
-       (UNQOPS:VSDQ_I_BHSI
-         (match_operand:VSDQ_I_BHSI 1 "register_operand" "w")))]
+  [(set (match_operand:VSDQ_I 0 "register_operand" "=w")
+       (UNQOPS:VSDQ_I
+         (match_operand:VSDQ_I 1 "register_operand" "w")))]
   "TARGET_SIMD"
   "s<optab>\\t%<v>0<Vmtype>, %<v>1<Vmtype>"
   [(set_attr "type" "neon_<optab><q>")]

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index a3c15ac3da2c0fab9f12b1ddad3d34b591cf8e11..75a62e522a0eac78412d2b22d5fe032fce9db7f9 100644 (file)
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -2318,6 +2318,12 @@ vqneg_s32 (int32x2_t __a)
   return (int32x2_t) __builtin_aarch64_sqnegv2si (__a);
 }
 
+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+vqneg_s64 (int64x1_t __a)
+{
+  return __builtin_aarch64_sqnegdi (__a);
+}
+
 __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
 vqnegq_s8 (int8x16_t __a)
 {
@@ -2354,6 +2360,12 @@ vqabs_s32 (int32x2_t __a)
   return (int32x2_t) __builtin_aarch64_sqabsv2si (__a);
 }
 
+__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+vqabs_s64 (int64x1_t __a)
+{
+  return __builtin_aarch64_sqabsdi (__a);
+}
+
 __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
 vqabsq_s8 (int8x16_t __a)
 {
@@ -20943,6 +20955,12 @@ vqabss_s32 (int32x1_t __a)
   return (int32x1_t) __builtin_aarch64_sqabssi (__a);
 }
 
+__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+vqabsd_s64 (int64_t __a)
+{
+  return __builtin_aarch64_sqabsdi (__a);
+}
+
 /* vqadd */
 
 __extension__ static __inline int8x1_t __attribute__ ((__always_inline__))
@@ -21561,6 +21579,12 @@ vqnegs_s32 (int32x1_t __a)
   return (int32x1_t) __builtin_aarch64_sqnegsi (__a);
 }
 
+__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+vqnegd_s64 (int64_t __a)
+{
+  return __builtin_aarch64_sqnegdi (__a);
+}
+
 /* vqrdmulh */
 
 __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 53f5e27d946bdfbc0e14a8ff034f47e3d32fecd3..908646d6823ab14fd3eeba728e8dee4349637430 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2014-04-22  Alex Velenko  <Alex.Velenko@arm.com>
+
+       * gcc.target/aarch64/vqneg_s64_1.c: New testcase.
+       * gcc.target/aarch64/vqabs_s64_1.c: New testcase.
+
 2014-04-22  Richard Sandiford  <rdsandiford@googlemail.com>
 
        * gcc.dg/memcpy-5.c: New test.

diff --git a/gcc/testsuite/gcc.target/aarch64/vqabs_s64_1.c b/gcc/testsuite/gcc.target/aarch64/vqabs_s64_1.c
new file mode 100644 (file)
index 0000000..3ea5322
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vqabs_s64_1.c
@@ -0,0 +1,54 @@
+/* Test vqabs_s64 intrinsics work correctly.  */
+/* { dg-do run } */
+/* { dg-options "--save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+int __attribute__ ((noinline))
+test_vqabs_s64 (int64x1_t passed, int64_t expected)
+{
+  return vget_lane_s64 (vqabs_s64 (passed), 0) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vqabsd_s64 (int64_t passed, int64_t expected)
+{
+  return vqabsd_s64 (passed) != expected;
+}
+
+/* { dg-final { scan-assembler-times "sqabs\\td\[0-9\]+, d\[0-9\]+" 2 } } */
+
+int
+main (int argc, char **argv)
+{
+  /* Basic test.  */
+  if (test_vqabs_s64 (vcreate_s64 (-1), 1))
+    abort ();
+  if (test_vqabsd_s64 (-1, 1))
+    abort ();
+
+  /* Getting absolute value of min int64_t.
+     Note, exact result cannot be represented in int64_t,
+     so max int64_t is expected.  */
+  if (test_vqabs_s64 (vcreate_s64 (0x8000000000000000), 0x7fffffffffffffff))
+    abort ();
+  if (test_vqabsd_s64 (0x8000000000000000, 0x7fffffffffffffff))
+    abort ();
+
+  /* Another input that gets max int64_t.  */
+  if (test_vqabs_s64 (vcreate_s64 (0x8000000000000001), 0x7fffffffffffffff))
+    abort ();
+  if (test_vqabsd_s64 (0x8000000000000001, 0x7fffffffffffffff))
+    abort ();
+
+  /* Checking that large positive numbers stay the same.  */
+  if (test_vqabs_s64 (vcreate_s64 (0x7fffffffffffffff), 0x7fffffffffffffff))
+    abort ();
+  if (test_vqabsd_s64 (0x7fffffffffffffff, 0x7fffffffffffffff))
+    abort ();
+
+  return 0;
+}
+/* { dg-final { cleanup-saved-temps } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/vqneg_s64_1.c b/gcc/testsuite/gcc.target/aarch64/vqneg_s64_1.c
new file mode 100644 (file)
index 0000000..a555b65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vqneg_s64_1.c
@@ -0,0 +1,47 @@
+/* Test vqneg_s64 intrinsics work correctly.  */
+/* { dg-do run } */
+/* { dg-options "--save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+int __attribute__ ((noinline))
+test_vqneg_s64 (int64x1_t passed, int64_t expected)
+{
+  return vget_lane_s64 (vqneg_s64 (passed), 0) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vqnegd_s64 (int64_t passed, int64_t expected)
+{
+  return vqnegd_s64 (passed) != expected;
+}
+
+/* { dg-final { scan-assembler-times "sqneg\\td\[0-9\]+, d\[0-9\]+" 2 } } */
+
+int
+main (int argc, char **argv)
+{
+  /* Basic test.  */
+  if (test_vqneg_s64 (vcreate_s64 (-1), 1))
+    abort ();
+  if (test_vqnegd_s64 (-1, 1))
+    abort ();
+
+  /* Negating max int64_t.  */
+  if (test_vqneg_s64 (vcreate_s64 (0x7fffffffffffffff), 0x8000000000000001))
+    abort ();
+  if (test_vqnegd_s64 (0x7fffffffffffffff, 0x8000000000000001))
+    abort ();
+
+  /* Negating min int64_t.
+     Note, exact negation cannot be represented as int64_t.  */
+  if (test_vqneg_s64 (vcreate_s64 (0x8000000000000000), 0x7fffffffffffffff))
+    abort ();
+  if (test_vqnegd_s64 (0x8000000000000000, 0x7fffffffffffffff))
+    abort ();
+
+  return 0;
+}
+/* { dg-final { cleanup-saved-temps } } */