mips.h (ISA_HAS_BBIT): New macro.

	* config/mips/mips.h (ISA_HAS_BBIT): New macro.
	* config/mips/mips.md (branch_likely): Remove const.  Fix
	comment formatting.
	(define_delay for type "branch"): Change to only apply for branch
	with likely variant.
	(define_delay for type "branch" and "branch_likely" no).  New delay
	definition.
	(equality_op): New code iterator.
	(bbv, bbinv): New code attributes.
	(*branch_bit<bbv><mode>, *branch_bit<bbv><mode>_inverted): New
	patterns.

testsuite/
	* gcc.target/mips/octeon-bbit-1.c: New test.
	* gcc.target/mips/octeon-bbit-2.c: New test.
	* gcc.target/mips/octeon-bbit-3.c: New test.

From-SVN: r139743

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5b0147c176fd57e9ae11e12068f64f695ce22d82..753422f2c470488ba09cac80f31c20f512e858c6 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2008-08-28  Adam Nemet  <anemet@caviumnetworks.com>
+
+       * config/mips/mips.h (ISA_HAS_BBIT): New macro.
+       * config/mips/mips.md (branch_likely): Remove const.  Fix
+       comment formatting.
+       (define_delay for type "branch"): Change to only apply for branch
+       with likely variant.
+       (define_delay for type "branch" and "branch_likely" no).  New delay
+       definition.
+       (equality_op): New code iterator.
+       (bbv, bbinv): New code attributes.
+       (*branch_bit<bbv><mode>, *branch_bit<bbv><mode>_inverted): New
+       patterns.
+
 2008-08-28  Manuel Lopez-Ibanez  <manu@gcc.gnu.org>
             Andrew Pinski  <pinskia@gcc.gnu.org>
 

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 14512e2e67e4a36183c596f71766bc99a1d6e302..66788c17e6ecdfa26edfca091082bbc9a78eaf13 100644 (file)
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1006,6 +1006,9 @@ enum mips_code_readable_setting {
    ? TARGET_LLSC && !TARGET_MIPS16     \
    : ISA_HAS_LL_SC)
 
+/* ISA includes the bbit* instructions.  */
+#define ISA_HAS_BBIT           TARGET_OCTEON
+
 /* ISA includes the pop instruction.  */
 #define ISA_HAS_POP            TARGET_OCTEON
 \f

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 84a44ee90d5226c78c0a887fae00a458de826932..0aba384144db8db2be7237f85c2977ccad33de8b 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -599,12 +599,12 @@
                (const_string "yes")
                (const_string "no")))
 
-;; Attribute defining whether or not we can use the branch-likely instructions
+;; Attribute defining whether or not we can use the branch-likely
+;; instructions.
 (define_attr "branch_likely" "no,yes"
-  (const
-   (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
-                (const_string "yes")
-                (const_string "no"))))
+  (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
+               (const_string "yes")
+               (const_string "no")))
 
 ;; True if an instruction might assign to hi or lo when reloaded.
 ;; This is used by the TUNE_MACC_CHAINS code.
@@ -788,6 +788,9 @@
 ;; by swapping the operands.
 (define_code_iterator swapped_fcond [ge gt unge ungt])
 
+;; Equality operators.
+(define_code_iterator equality_op [eq ne])
+
 ;; These code iterators allow the signed and unsigned scc operations to use
 ;; the same template.
 (define_code_iterator any_gt [gt gtu])
@@ -848,6 +851,12 @@
                                 (unge "ule")
                                 (ungt "ult")])
 
+;; The value of the bit when the branch is taken for branch_bit patterns.
+;; Comparison is always against zero so this depends on the operator.
+(define_code_attr bbv [(eq "0") (ne "1")])
+
+;; This is the inverse value of bbv.
+(define_code_attr bbinv [(eq "1") (ne "0")])
 \f
 ;; .........................
 ;;
@@ -856,11 +865,19 @@
 ;; .........................
 
 (define_delay (and (eq_attr "type" "branch")
-                  (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
+                  (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
+                  (eq_attr "branch_likely" "yes"))
+  [(eq_attr "can_delay" "yes")
+   (nil)
+   (eq_attr "can_delay" "yes")])
+
+;; Branches that don't have likely variants do not annul on false.
+(define_delay (and (eq_attr "type" "branch")
+                  (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
+                  (eq_attr "branch_likely" "no"))
   [(eq_attr "can_delay" "yes")
    (nil)
-   (and (eq_attr "branch_likely" "yes")
-       (eq_attr "can_delay" "yes"))])
+   (nil)])
 
 (define_delay (eq_attr "type" "jump")
   [(eq_attr "can_delay" "yes")
@@ -5052,6 +5069,50 @@
        (if_then_else (match_operand 0)
                      (label_ref (match_operand 1))
                      (pc)))])
+
+;; Branch if bit is set/clear.
+
+(define_insn "*branch_bit<bbv><mode>"
+  [(set (pc)
+       (if_then_else
+        (equality_op (zero_extract:GPR
+                      (match_operand:GPR 1 "register_operand" "d")
+                      (const_int 1)
+                      (match_operand 2 "const_int_operand" ""))
+                     (const_int 0))
+        (label_ref (match_operand 0 ""))
+        (pc)))]
+  "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
+{
+  return
+    mips_output_conditional_branch (insn, operands,
+                                   MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
+                                   MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
+}
+  [(set_attr "type"         "branch")
+   (set_attr "mode"         "none")
+   (set_attr "branch_likely" "no")])
+
+(define_insn "*branch_bit<bbv><mode>_inverted"
+  [(set (pc)
+       (if_then_else
+        (equality_op (zero_extract:GPR
+                      (match_operand:GPR 1 "register_operand" "d")
+                      (const_int 1)
+                      (match_operand 2 "const_int_operand" ""))
+                     (const_int 0))
+        (pc)
+        (label_ref (match_operand 0 ""))))]
+  "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
+{
+  return
+    mips_output_conditional_branch (insn, operands,
+                                   MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
+                                   MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
+}
+  [(set_attr "type"         "branch")
+   (set_attr "mode"         "none")
+   (set_attr "branch_likely" "no")])
 \f
 ;;
 ;;  ....................

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ccc35c83d1436815f4c764d2705e8c32df09df32..23ea3b5c12dd0e08daf921e84db3d5c4a67081db 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2008-08-28  Adam Nemet  <anemet@caviumnetworks.com>
+
+       * gcc.target/mips/octeon-bbit-1.c: New test.
+       * gcc.target/mips/octeon-bbit-2.c: New test.
+       * gcc.target/mips/octeon-bbit-3.c: New test.
+
 2008-08-28  Manuel Lopez-Ibanez  <manu@gcc.gnu.org>
             Andrew Pinski  <pinskia@gcc.gnu.org>
 

diff --git a/gcc/testsuite/gcc.target/mips/octeon-bbit-1.c b/gcc/testsuite/gcc.target/mips/octeon-bbit-1.c
new file mode 100644 (file)
index 0000000..24fd728
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/octeon-bbit-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-mips-options "-O2 -march=octeon" } */
+/* { dg-final { scan-assembler-times "\tbbit1\t" 4 } } */
+/* { dg-final { scan-assembler-times "\tbbit0\t" 2 } } */
+/* { dg-final { scan-assembler-not "andi\t" } } */
+
+NOMIPS16 void
+f1 (long long i)
+{
+  if (i & 0x80)
+    foo ();
+}
+
+NOMIPS16 void
+f2 (int i)
+{
+  if (!(i & 0x80))
+    foo ();
+}
+
+NOMIPS16 void
+f3 (int i)
+{
+  if (i % 2)
+    foo ();
+}
+
+NOMIPS16 void
+f4 (int i)
+{
+  if (i & 1)
+    foo ();
+}
+
+NOMIPS16 void
+f5 (long long i)
+{
+  if ((i >> 3) & 1)
+    foo ();
+}
+
+unsigned long long r;
+
+NOMIPS16 static inline __attribute__((always_inline)) int
+test_bit(unsigned long long nr, const unsigned long long *addr)
+{
+  return 1UL & (addr[nr >> 6] >> (nr & 63ULL));
+}
+
+NOMIPS16 void
+f6 ()
+{
+  if (!test_bit(0, &r))
+    g ();
+}

diff --git a/gcc/testsuite/gcc.target/mips/octeon-bbit-2.c b/gcc/testsuite/gcc.target/mips/octeon-bbit-2.c
new file mode 100644 (file)
index 0000000..6be7ef5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/octeon-bbit-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-mips-options "-O2 -march=octeon -mbranch-likely" } */
+/* { dg-final { scan-assembler "\tbbit\[01\]\t" } } */
+/* { dg-final { scan-assembler-not "\tbbit\[01\]l\t" } } */
+/* { dg-final { scan-assembler "\tbnel\t" } } */
+/* { dg-final { scan-assembler-not "\tbne\t" } } */
+
+NOMIPS16 int
+f (int n, int i)
+{
+  int s = 0;
+  for (; i & 1; i++)
+    s += i;
+  return s;
+}
+
+NOMIPS16 int
+g (int n, int i)
+{
+  int s = 0;
+  for (i = 0; i < n; i++)
+    s += i;
+  return s;
+}

diff --git a/gcc/testsuite/gcc.target/mips/octeon-bbit-3.c b/gcc/testsuite/gcc.target/mips/octeon-bbit-3.c
new file mode 100644 (file)
index 0000000..ac8d0ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/octeon-bbit-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-mips-options "-O2 -march=octeon" } */
+/* { dg-final { scan-assembler-times "\tbbit\[01\]\t|\tbgez\t" 2 } } */
+/* { dg-final { scan-assembler-not "ext\t" } } */
+
+void abort (void);
+void exit (int);
+
+typedef unsigned long long ulong64;
+
+typedef struct bitfield_s {
+  ulong64 a:1;
+  ulong64 b:29;
+  ulong64 c:1;
+  ulong64 d:15;
+  ulong64 f:18;
+} bitfield_t;
+
+bitfield_t bar;
+
+NOMIPS16 void
+f ()
+{
+  foo(&bar);
+  if (bar.a != 0x1)
+    abort ();
+  else if (!bar.c)
+    abort ();
+  else
+    exit (0);
+}