drm/i915/irq: use a dedicated IMR cache for VLV/CHV

There are three groups of platforms using i915->irq_mask independently:
gen 2-4, VLV/CHV, and gen 5-7.

The VLV/CHV usage is purely limited to display. Move its irq_mask usage
to struct intel_display as vlv_imr_mask for VLV/CHV.

vlv_imr_mask could be put inside a union with de_irq_mask[], but keep
them separate to avoid accidental aliasing of the values.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/cef6dee8d0b02ff76180c5879f3056e102947a57.1758198300.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 791021a4e3bb040f3d9df65df23410bc82c68bdc..48a707557c2976aed53e5f16fb49003df893217e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -475,6 +475,11 @@ struct intel_display {
 
                struct work_struct vblank_notify_work;
 
+               /*
+                * Cached value of VLV/CHV IMR to avoid reads in updating the
+                * bitfield.
+                */
+               u32 vlv_imr_mask;
                u32 de_irq_mask[I915_MAX_PIPES];
                u32 pipestat_irq_mask[I915_MAX_PIPES];
        } irq;

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 123e054affbe9fc7068246bcbc6b85b082619a75..df718670546b44ce05760103374a1b29cc767af7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1865,8 +1865,6 @@ void vlv_display_error_irq_handler(struct intel_display *display,
 
 static void _vlv_display_irq_reset(struct intel_display *display)
 {
-       struct drm_i915_private *dev_priv = to_i915(display->drm);
-
        if (display->platform.cherryview)
                intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
        else
@@ -1881,7 +1879,7 @@ static void _vlv_display_irq_reset(struct intel_display *display)
        i9xx_pipestat_irq_reset(display);
 
        intel_display_irq_regs_reset(display, VLV_IRQ_REGS);
-       dev_priv->irq_mask = ~0u;
+       display->irq.vlv_imr_mask = ~0u;
 }
 
 void vlv_display_irq_reset(struct intel_display *display)
@@ -1939,7 +1937,6 @@ static u32 vlv_error_mask(void)
 
 static void _vlv_display_irq_postinstall(struct intel_display *display)
 {
-       struct drm_i915_private *dev_priv = to_i915(display->drm);
        u32 pipestat_mask;
        u32 enable_mask;
        enum pipe pipe;
@@ -1973,11 +1970,11 @@ static void _vlv_display_irq_postinstall(struct intel_display *display)
                enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
                        I915_LPE_PIPE_C_INTERRUPT;
 
-       drm_WARN_ON(display->drm, dev_priv->irq_mask != ~0u);
+       drm_WARN_ON(display->drm, display->irq.vlv_imr_mask != ~0u);
 
-       dev_priv->irq_mask = ~enable_mask;
+       display->irq.vlv_imr_mask = ~enable_mask;
 
-       intel_display_irq_regs_init(display, VLV_IRQ_REGS, dev_priv->irq_mask, enable_mask);
+       intel_display_irq_regs_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask);
 }
 
 void vlv_display_irq_postinstall(struct intel_display *display)