Also treat model numbers 0x5a/0x5d as Silvermont

diff --git a/ChangeLog b/ChangeLog
index c199a5d93849e34b56fd8aa797ed8d653a3798a3..d746e18d59a035ced96ee3497ac3f065aad2016b 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,7 +1,8 @@
 2015-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 
        * sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features):
-       Treat model numbers 0x4a/0x4d as Intel Silvermont architecture.
+       Treat model numbers 0x4a/0x4d/0x5a/0x5d as Intel Silvermont
+       architecture.
 
 2015-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 

diff --git a/sysdeps/x86_64/multiarch/init-arch.c b/sysdeps/x86_64/multiarch/init-arch.c
index ec71918b254ced939d3f80cf0ce1d341f61a38bd..9299360612fc422a29f7b6aef113ae0275a24f74 100644 (file)
--- a/sysdeps/x86_64/multiarch/init-arch.c
+++ b/sysdeps/x86_64/multiarch/init-arch.c
@@ -81,6 +81,8 @@ __init_cpu_features (void)
            case 0x37:
            case 0x4a:
            case 0x4d:
+           case 0x5a:
+           case 0x5d:
              /* Unaligned load versions are faster than SSSE3
                 on Silvermont.  */
 #if index_Fast_Unaligned_Load != index_Prefer_PMINUB_for_stringop