fpga: zynqmp: Add support to load PL bistream

Update PL bitstream load support by updating the
smc arguments as per latest ATF changes.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index dcb4544574e2e9b293c38ea833edeb604f9d6a30..b5492d42e03a14abc481c29cd96ecad3e3dc91f0 100644 (file)
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -204,17 +204,12 @@ static int invoke_smc(ulong id, ulong reg0, ulong reg1, ulong reg2)
        return regs.regs[0];
 }
 
-static int zynqmp_info(xilinx_desc *desc)
-{
-       debug("%s called!\n", __func__);
-       return invoke_smc(ZYNQMP_SIP_SVC_CSU_DMA_INFO, 0, 0, 0);
-}
-
 static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
                     bitstream_type bstype)
 {
        u32 swap;
-       ulong bin_buf;
+       ulong bin_buf, flags;
+       int ret;
 
        if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
                return FPGA_FAIL;
@@ -223,17 +218,21 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
 
        debug("%s called!\n", __func__);
        flush_dcache_range(bin_buf, bin_buf + bsize);
-       return invoke_smc(ZYNQMP_SIP_SVC_CSU_DMA_LOAD, bin_buf, bsize, bstype);
-}
 
-static int zynqmp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
-{
-       debug("%s called!\n", __func__);
-       return invoke_smc(ZYNQMP_SIP_SVC_CSU_DMA_DUMP, (u64)buf, bsize, 0);
+       if (bsize % 4)
+               bsize = bsize/4 + 1;
+       else
+               bsize = bsize/4;
+
+       flags = (u32)bsize | ((u64)bstype << 32);
+
+       ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, bin_buf, flags, 0);
+       if (ret)
+               debug("PL FPGA LOAD fail\n");
+
+       return ret;
 }
 
 struct xilinx_fpga_op zynqmp_op = {
        .load = zynqmp_load,
-       .dump = zynqmp_dump,
-       .info = zynqmp_info,
 };

diff --git a/include/zynqmppl.h b/include/zynqmppl.h
index e14a9dc06968174eee9d12c33a8e47c6bd37ae97..048ee284ea34d223820fd72504d87fcb63cb4be0 100644 (file)
--- a/include/zynqmppl.h
+++ b/include/zynqmppl.h
@@ -10,11 +10,13 @@
 
 #include <xilinx.h>
 
-#define ZYNQMP_SIP_SVC_CSU_DMA_INFO            0x82002004
-#define ZYNQMP_SIP_SVC_CSU_DMA_LOAD            0x82002005
-#define ZYNQMP_SIP_SVC_CSU_DMA_DUMP            0x82002006
 #define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID          0x82002007
 
+#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD            0xC2000016
+#define ZYNQMP_FPGA_OP_INIT                    (1 << 0)
+#define ZYNQMP_FPGA_OP_LOAD                    (1 << 1)
+#define ZYNQMP_FPGA_OP_DONE                    (1 << 2)
+
 extern struct xilinx_fpga_op zynqmp_op;
 
 #define XILINX_ZYNQMP_DESC \