arm64: dts: renesas: r9a09g077: Add pinctrl node

Add pinctrl node to RZ/T2H ("R9A09G077") SoC DTSI.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250812200344.3253781-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 8ee88b8e8f3302007180526ea4b2e7b797bd01f0..0929ce2db05c33b6074fd3e002b60186714d9a49 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -216,6 +216,19 @@
                        #power-domain-cells = <0>;
                };
 
+               pinctrl: pinctrl@802c0000 {
+                       compatible = "renesas,r9a09g077-pinctrl";
+                       reg = <0 0x802c0000 0 0x10000>,
+                             <0 0x812c0000 0 0x10000>,
+                             <0 0x802b0000 0 0x10000>;
+                       reg-names = "nsr", "srs", "srn";
+                       clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pinctrl 0 0 288>;
+                       power-domains = <&cpg>;
+               };
+
                gic: interrupt-controller@83000000 {
                        compatible = "arm,gic-v3";
                        reg = <0x0 0x83000000 0 0x40000>,