sunxi: a133: dram: Align parameters terminology with Allwinner

There is a mistmatch between Allwinner's dram_para BSP definitions and the
parameters names in mainline u-boot for TPR1-3. What we call TPR1 is actually
MR22 while TPR2 is TPR0 and TPR3 is TPR1. MR22 does get written to the
corresponding register. This only concerns LPDDR4 support.

Introduce a new Kconfig entry for MR22 and proceed with the rename.
Update the only config currently using it.

See the list of parameters from the Allwinner BSP at the end of:
https://linux-sunxi.org/A133/DRAMC

Note that the H616/H6 code is coherent with this new TPR0 definition
(and does not use TPR1 and MR22).

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Sponsored-by: MEC Electronics GmbH <https://www.mec.at/>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h
index a5fc6ad36560b8c66431b97294e96dbec211c624..01f2214cd15787da725fe5eb6c69c379ace1f33c 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h
@@ -205,6 +205,8 @@ struct dram_para {
        uint32_t mr12;
        uint32_t mr13;
        uint32_t mr14;
+       uint32_t mr22;
+       uint32_t tpr0;
        uint32_t tpr1;
        uint32_t tpr2;
        uint32_t tpr3;

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index a60ebe1d964c05f2cdec3fdaa6f10f3b48aacb90..89f0e77bcdb775f7f76acd16fe8b6859014f600a 100644 (file)
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -118,6 +118,13 @@ config DRAM_SUNXI_MR14
        help
          MR14 value from vendor DRAM settings.
 
+config DRAM_SUNXI_MR22
+       hex "DRAM MR22 parameter"
+       depends on DRAM_SUN50I_A133
+       default 0x0
+       help
+         MR22 value from vendor DRAM settings.
+
 config DRAM_SUNXI_TPR0
        hex "DRAM TPR0 parameter"
        default 0x0

diff --git a/arch/arm/mach-sunxi/dram_sun50i_a133.c b/arch/arm/mach-sunxi/dram_sun50i_a133.c
index e5c46e036cbb1da09ca40b48faf43797e51599fa..ca3e2513c69a0e43913bc57612086c0fa5f3fef6 100644 (file)
--- a/arch/arm/mach-sunxi/dram_sun50i_a133.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_a133.c
@@ -426,8 +426,8 @@ static void mctl_drive_odt_config(const struct dram_para *para)
 
                writel_relaxed(val, base);
                if (para->type == SUNXI_DRAM_TYPE_LPDDR4) {
-                       if (para->tpr3 & 0x1f1f1f1f)
-                               val = (para->tpr3 >> (i * 8)) & 0x1f;
+                       if (para->tpr1 & 0x1f1f1f1f)
+                               val = (para->tpr1 >> (i * 8)) & 0x1f;
                        else
                                val = 4;
                }
@@ -468,7 +468,7 @@ static void mctl_phy_ca_bit_delay_compensation(const struct dram_para *para)
        u32 *ptr;
 
        if (para->tpr10 & BIT(31)) {
-               val = para->tpr2;
+               val = para->tpr0;
        } else {
                val = ((para->tpr10 << 1) & 0x1e) |
                      ((para->tpr10 << 5) & 0x1e00) |
@@ -781,7 +781,7 @@ static void mctl_dfi_init(const struct dram_para *para)
                mctl_mr_write_lpddr4(12, para->mr12);
                mctl_mr_write_lpddr4(13, para->mr13);
                mctl_mr_write_lpddr4(14, para->mr14);
-               mctl_mr_write_lpddr4(22, para->tpr1);
+               mctl_mr_write_lpddr4(22, para->mr22);
                break;
        }
 
@@ -1182,7 +1182,6 @@ static const struct dram_para para = {
 #elif defined(CONFIG_SUNXI_DRAM_LPDDR4)
        .type = SUNXI_DRAM_TYPE_LPDDR4,
 #endif
-       /* TODO: Populate from config */
        .dx_odt = CONFIG_DRAM_SUNXI_DX_ODT,
        .dx_dri = CONFIG_DRAM_SUNXI_DX_DRI,
        .ca_dri = CONFIG_DRAM_SUNXI_CA_DRI,
@@ -1191,9 +1190,10 @@ static const struct dram_para para = {
        .mr12 = CONFIG_DRAM_SUNXI_MR12,
        .mr13 = CONFIG_DRAM_SUNXI_MR13,
        .mr14 = CONFIG_DRAM_SUNXI_MR14,
+       .mr22 = CONFIG_DRAM_SUNXI_MR22,
+       .tpr0 = CONFIG_DRAM_SUNXI_TPR0,
        .tpr1 = CONFIG_DRAM_SUNXI_TPR1,
        .tpr2 = CONFIG_DRAM_SUNXI_TPR2,
-       .tpr3 = CONFIG_DRAM_SUNXI_TPR3,
        .tpr6 = CONFIG_DRAM_SUNXI_TPR6,
        .tpr10 = CONFIG_DRAM_SUNXI_TPR10,
        .tpr11 = CONFIG_DRAM_SUNXI_TPR11,

diff --git a/configs/liontron-h-a133l_defconfig b/configs/liontron-h-a133l_defconfig
index 56c5262f26788eaea3f03f2cd5ca2f2b537f4a13..831d5b56e3a743744e738f4a50cd285a97f8b3fd 100644 (file)
--- a/configs/liontron-h-a133l_defconfig
+++ b/configs/liontron-h-a133l_defconfig
@@ -10,9 +10,9 @@ CONFIG_DRAM_SUNXI_PARA0=0xd0a050c
 CONFIG_DRAM_SUNXI_MR11=0x4
 CONFIG_DRAM_SUNXI_MR12=0x72
 CONFIG_DRAM_SUNXI_MR14=0x7
-CONFIG_DRAM_SUNXI_TPR1=0x26
-CONFIG_DRAM_SUNXI_TPR2=0x6060606
-CONFIG_DRAM_SUNXI_TPR3=0x84040404
+CONFIG_DRAM_SUNXI_MR22=0x26
+CONFIG_DRAM_SUNXI_TPR0=0x6060606
+CONFIG_DRAM_SUNXI_TPR1=0x84040404
 CONFIG_DRAM_SUNXI_TPR6=0x48000000
 CONFIG_DRAM_SUNXI_TPR10=0x273333
 CONFIG_DRAM_SUNXI_TPR11=0x231d151c