drm/amd/pm/ci: Disable MCLK DPM on problematic CI ASICs

There are two known cases where MCLK DPM can causes issues:

Radeon R9 M380 found in iMac computers from 2015.
The SMU in this GPU just hangs as soon as we send it the
PPSMC_MSG_MCLKDPM_Enable command, even when MCLK switching is
disabled, and even when we only populate one MCLK DPM level.
Apply workaround to all devices with the same subsystem ID.

Radeon R7 260X due to old memory controller microcode.
We only flash the MC ucode when it isn't set up by the VBIOS,
therefore there is no way to make sure that it has the correct
ucode version.

I verified that this patch fixes the SMU hang on the R9 M380
which would previously fail to boot. This also fixes the UVD
initialization error on that GPU which happened because the
SMU couldn't ungate the UVD after it hung.

Fixes: 86457c3b21cb ("drm/amd/powerplay: Add support for CI asics to hwmgr")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c
index 2b5ac21fee39970da04bd55f80e08e876ae5dadc..1d6e30269d5679bf7dd503520ac84e712463bba4 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c
@@ -104,6 +104,21 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
                                         PP_GFXOFF_MASK);
                hwmgr->pp_table_version = PP_TABLE_V0;
                hwmgr->od_enabled = false;
+               switch (hwmgr->chip_id) {
+               case CHIP_BONAIRE:
+                       /* R9 M380 in iMac 2015: SMU hangs when enabling MCLK DPM
+                        * R7 260X cards with old MC ucode: MCLK DPM is unstable
+                        */
+                       if (adev->pdev->subsystem_vendor == 0x106B ||
+                           adev->pdev->device == 0x6658) {
+                               dev_info(adev->dev, "disabling MCLK DPM on quirky ASIC");
+                               adev->pm.pp_feature &= ~PP_MCLK_DPM_MASK;
+                               hwmgr->feature_mask &= ~PP_MCLK_DPM_MASK;
+                       }
+                       break;
+               default:
+                       break;
+               }
                smu7_init_function_pointers(hwmgr);
                break;
        case AMDGPU_FAMILY_CZ: