zynqmp: Add support for Veloce 4.0

Veloce has some limitation:
- uart clk based on tests is 96kHz
- arm architected timers runs at 20kHz
- MMC is not working and it is disabled
- Uart is working on 9600bps

Show 1Mhz as ARM frequency through bdinfo instead
of 0Mhz.

Clock is not fully clear that's why u-boot can detect
Veloce platform in range of 0 to 1MHz.
Linux kernel images are already loaded to the memory
that's why specific veloce variable is added
and also setup as boot command.

9600bsp is baudrate which is valid for Veloce.
serial_init is called so early that's why serial driver
checking input frequency and based on that setup
correct baudrate. Setting up via variables is not possible.

Change bootargs handling to preboot where proper kernel
command line is setup with correct baudrate setting.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c
index e9083e03d8d8bfc4100ff30088539696f78b3341..290f795ae76947393c24ec729f9243847f3e11b0 100644 (file)
--- a/arch/arm/cpu/armv8/zynqmp/clk.c
+++ b/arch/arm/cpu/armv8/zynqmp/clk.c
@@ -17,7 +17,7 @@ unsigned long get_uart_clk(int dev_id)
 
        switch (ver) {
        case ZYNQMP_CSU_VERSION_VELOCE:
-               return 400000;
+               return 96000;
        case ZYNQMP_CSU_VERSION_EP108:
                return 25000000;
        }
@@ -38,7 +38,12 @@ int set_cpu_clk_info(void)
 {
        gd->cpu_clk = get_tbclk();
 
-       gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+       /* Support Veloce to show at least 1MHz via bdi */
+       if (gd->cpu_clk > 1000000)
+               gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+       else
+               gd->bd->bi_arm_freq = 1;
+
        gd->bd->bi_dsp_freq = 0;
 
        return 0;

diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index 2353ec2180c50615ea0266ca56aeb6abe61059fd..77fd4f19d9dc8a2b6e57af58661f2b69f65b9fc9 100644 (file)
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -17,8 +17,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 unsigned int zynqmp_get_silicon_version(void)
 {
+       gd->cpu_clk = get_tbclk();
+
        switch (gd->cpu_clk) {
-       case 400000:
+       case 0 ... 1000000:
                return ZYNQMP_CSU_VERSION_VELOCE;
        case 50000000:
                return ZYNQMP_CSU_VERSION_QEMU;

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 9254f93650cd4a1c3b85775dd3e669788824c7e5..efc269128d6cf22ee81e13d05c8fb36c49d8b691 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -80,15 +80,19 @@ int board_eth_init(bd_t *bis)
 int board_mmc_init(bd_t *bd)
 {
        int ret = 0;
+       u32 ver = zynqmp_get_silicon_version();
 
+       if (ver != ZYNQMP_CSU_VERSION_VELOCE) {
 #if defined(CONFIG_ZYNQ_SDHCI)
 # if defined(CONFIG_ZYNQ_SDHCI0)
-        ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
+               ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
 # endif
 # if defined(CONFIG_ZYNQ_SDHCI1)
-        ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
+               ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
 # endif
 #endif
+       }
+
         return ret;
 }
 #endif
@@ -106,6 +110,8 @@ int board_late_init(void)
 
        switch (ver) {
        case ZYNQMP_CSU_VERSION_VELOCE:
+               setenv("baudrate", "9600");
+               setenv("bootcmd", "run veloce");
        case ZYNQMP_CSU_VERSION_EP108:
                setenv("serverip", "10.10.70.101");
                setenv("ipaddr", "10.10.71.100");

diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 74c449663bc7881fea9e59f649d30f85349ad5da..f8b84f53852777d816f5ea889cb64dcc3d531740 100644 (file)
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -48,10 +48,16 @@ static void uart_zynq_serial_setbrg(const int port)
        /* Calculation results. */
        unsigned int calc_bauderror, bdiv, bgen;
        unsigned long calc_baud = 0;
-       unsigned long baud = gd->baudrate;
+       unsigned long baud;
        unsigned long clock = get_uart_clk(port);
        struct uart_zynq *regs = uart_zynq_ports[port];
 
+       /* Covering case where input clock is so slow */
+       if (clock < 1000000 && gd->baudrate > 9600) {
+               gd->baudrate = 9600;
+       }
+       baud = gd->baudrate;
+
        /*                master clock
         * Baud rate = ------------------
         *              bgen * (bdiv + 1)

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 96024a2c5e042e35261ecc43e29898a95634c094..6a24af53c8e1375a49858961866ff5c16310aada 100644 (file)
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -136,6 +136,10 @@
        "initrd_size=0x2000000\0"       \
        "fdt_addr=0x100000\0"           \
        "fdt_high=0x10000000\0"         \
+       "veloce=fdt addr f000000 && fdt set /amba/misc_clk clock-frequency <96000> && "\
+       "fdt set /amba_apu/timer clock-frequency <480000> && " \
+       "fdt set /amba/i2c_clk clock-frequency <480000> && " \
+       "booti 80000 - f000000\0"       \
        "netboot=tftpboot 80000 Image && tftpboot f000000 system.dtb && booti 80000 - f000000\0"        \
        "qspiboot=sf probe 0 && sf read f000000 100000 40000 && "       \
                  "sf read 80000 140000 1800000 && booti 80000 - f000000\0"     \
@@ -143,8 +147,9 @@
                "fatload mmc 0:0 f000000 Image && booti 80000 - f000000\0"      \
        "jtagboot=tftpboot 10000000 image.ub && bootm\0"
 
-#define CONFIG_BOOTARGS                "console=ttyPS0,115200 earlycon=cdns,mmio,0xff000000,115200n8"
-#define CONFIG_BOOTCOMMAND     "echo Hello Xilinx ZynqMP; run $modeboot"
+#define CONFIG_BOOTARGS                "setenv bootargs console=ttyPS0,${baudrate} earlycon=cdns,mmio,0xff000000,${baudrate}n8"
+#define CONFIG_PREBOOT         "echo Hello Xilinx ZynqMP; run bootargs"
+#define CONFIG_BOOTCOMMAND     "run $modeboot"
 #define CONFIG_BOOTDELAY       5
 
 #define CONFIG_BOARD_LATE_INIT