* config/alpha/alpha.c: Fix comment typos.
* config/alpha/alpha.md: Likewise.
* config/arm/arm.c: Likewise.
* config/arm/arm.md: Likewise.
* config/arm/lib1funcs.asm: Likewise.
* config/avr/avr.md: Likewise.
* config/arm/README-interworking: Fix typos.
From-SVN: r69277
+2003-07-12 Kazu Hirata <kazu@cs.umass.edu>
+
+ * config/alpha/alpha.c: Fix comment typos.
+ * config/alpha/alpha.md: Likewise.
+ * config/arm/arm.c: Likewise.
+ * config/arm/arm.md: Likewise.
+ * config/arm/lib1funcs.asm: Likewise.
+ * config/avr/avr.md: Likewise.
+ * config/arm/README-interworking: Fix typos.
+
2003-07-12 Kazu Hirata <kazu@cs.umass.edu>
* c-format.c: Fix comment formatting.
flag_pic = 0;
}
- /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
+ /* On Unicos/Mk, the native compiler consistently generates /d suffices for
floating-point instructions. Make that the default for this target. */
if (TARGET_ABI_UNICOSMK)
alpha_fprm = ALPHA_FPRM_DYN;
be shared. */
if (f == 0 && exact_log2 (diff) > 0
- /* On EV6, we've got enough shifters to make non-arithmatic shifts
+ /* On EV6, we've got enough shifters to make non-arithmetic shifts
viable over a longer latency cmove. On EV5, the E0 slot is a
scarce resource, and on EV4 shift has the same latency as a cmove. */
&& (diff <= 8 || alpha_cpu == PROCESSOR_EV6))
For EV4, loads can be issued to either IB0 or IB1, thus we have 2
alternative schedules. For EV5, we can choose between E0/E1 and
- FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */
+ FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
static int
alpha_multipass_dfa_lookahead (void)
;; The ROUND_SUFFIX attribute marks which instructions require a
;; rounding-mode suffix. The value NONE indicates no suffix,
-;; the value NORMAL indicates a suffix controled by alpha_fprm.
+;; the value NORMAL indicates a suffix controlled by alpha_fprm.
(define_attr "round_suffix" "none,normal,c"
(const_string "none"))
;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
;;
-;; The actual suffix emitted is controled by alpha_fptm.
+;; The actual suffix emitted is controlled by alpha_fptm.
(define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
(const_string "none"))
(where <name> is the name of the function) which indicates the start
of the Thumb code. This does have the interesting side effect in that
if this function is now called from a Thumb mode piece of code
-outsside of the current file, the linker will generate a calling stub
+outside of the current file, the linker will generate a calling stub
to switch from Thumb mode into ARM mode, and then this is immediately
overridden by the function's header which switches back into Thumb
mode.
{ NULL, 0 }
};
-/* This is a magic stucture. The 'string' field is magically filled in
+/* This is a magic structure. The 'string' field is magically filled in
with a pointer to the value specified by the user on the command line
assuming that the user has specified such a value. */
return VALID_IWMMXT_REG_MODE (mode);
if (regno <= LAST_ARM_REGNUM)
- /* We allow any value to be stored in the general regisetrs. */
+ /* We allow any value to be stored in the general registers. */
return 1;
if ( regno == FRAME_POINTER_REGNUM
&& get_attr_far_jump (insn) == FAR_JUMP_YES
)
{
- /* Record the fact that we have decied that
+ /* Record the fact that we have decided that
the function does use far jumps. */
cfun->machine->far_jump_used = 1;
return 1;
; and stack frame generation. Operand 0 is the
; register to "use".
(UNSPEC_CHECK_ARCH 7); Set CCs to indicate 26-bit or 32-bit mode.
- (UNSPEC_WSHUFH 8) ; Used by the instrinsic form of the iWMMXt WSHUFH instruction.
- (UNSPEC_WACC 9) ; Used by the instrinsic form of the iWMMXt WACC instruction.
- (UNSPEC_TMOVMSK 10) ; Used by the instrinsic form of the iWMMXt TMOVMSK instruction.
- (UNSPEC_WSAD 11) ; Used by the instrinsic form of the iWMMXt WSAD instruction.
- (UNSPEC_WSADZ 12) ; Used by the instrinsic form of the iWMMXt WSADZ instruction.
- (UNSPEC_WMACS 13) ; Used by the instrinsic form of the iWMMXt WMACS instruction.
- (UNSPEC_WMACU 14) ; Used by the instrinsic form of the iWMMXt WMACU instruction.
- (UNSPEC_WMACSZ 15) ; Used by the instrinsic form of the iWMMXt WMACSZ instruction.
- (UNSPEC_WMACUZ 16) ; Used by the instrinsic form of the iWMMXt WMACUZ instruction.
- (UNSPEC_CLRDI 17) ; Used by the instrinsic form of the iWMMXt CLRDI instruction.
- (UNSPEC_WMADDS 18) ; Used by the instrinsic form of the iWMMXt WMADDS instruction.
- (UNSPEC_WMADDU 19) ; Used by the instrinsic form of the iWMMXt WMADDU instruction.
+ (UNSPEC_WSHUFH 8) ; Used by the intrinsic form of the iWMMXt WSHUFH instruction.
+ (UNSPEC_WACC 9) ; Used by the intrinsic form of the iWMMXt WACC instruction.
+ (UNSPEC_TMOVMSK 10) ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction.
+ (UNSPEC_WSAD 11) ; Used by the intrinsic form of the iWMMXt WSAD instruction.
+ (UNSPEC_WSADZ 12) ; Used by the intrinsic form of the iWMMXt WSADZ instruction.
+ (UNSPEC_WMACS 13) ; Used by the intrinsic form of the iWMMXt WMACS instruction.
+ (UNSPEC_WMACU 14) ; Used by the intrinsic form of the iWMMXt WMACU instruction.
+ (UNSPEC_WMACSZ 15) ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.
+ (UNSPEC_WMACUZ 16) ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.
+ (UNSPEC_CLRDI 17) ; Used by the intrinsic form of the iWMMXt CLRDI instruction.
+ (UNSPEC_WMADDS 18) ; Used by the intrinsic form of the iWMMXt WMADDS instruction.
+ (UNSPEC_WMADDU 19) ; Used by the intrinsic form of the iWMMXt WMADDU instruction.
]
)
; Only model the write buffer for ARM6 and ARM7. Earlier processors don't
; have one. Later ones, such as StrongARM, have write-back caches, so don't
-; suffer blockages enough to warrent modelling this (and it can adversely
+; suffer blockages enough to warrant modelling this (and it can adversely
; affect the schedule).
(define_attr "model_wbuf" "no,yes" (const (symbol_ref "arm_is_6_or_7")))
\f
;; Compare & branch insns
-;; The range calcualations are based as follows:
+;; The range calculations are based as follows:
;; For forward branches, the address calculation returns the address of
;; the next instruction. This is 2 beyond the branch instruction.
;; For backward branches, the address calculation returns the address of
pc .req r15
#endif
/* ------------------------------------------------------------------------ */
-/* Bodies of the divsion and modulo routines. */
+/* Bodies of the division and modulo routines. */
/* ------------------------------------------------------------------------ */
.macro ARM_DIV_MOD_BODY modulo
LSYM(Loop1):
;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-;; This instructin sets Z flag
+;; This instruction sets Z flag
(define_insn "sez"
[(set (cc0) (const_int 0))]
projects / thirdparty / gcc.git / commitdiff
