drm/tidss: dispc: Switch OVR_REG_FLD_MOD to using a mask

The OVR_REG_FLD_MOD function takes the start and end bits as parameter
and will generate a mask out of them.

This makes it difficult to share the masks between callers, since we now
need two arguments and to keep them consistent.

Let's change OVR_REG_FLD_MOD to take the mask as an argument instead,
and let the caller create the mask. Eventually, this mask will be moved
to a define.

Signed-off-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20250827-drm-tidss-field-api-v3-13-7689b664cc63@kernel.org
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index 0255f7156f46008c8fee2b37f1431957f1c71cad..9ecbea60d37cf981c8ce00f075f19f925cce44be 100644 (file)
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -632,13 +632,13 @@ void tidss_disable_oldi(struct tidss_device *tidss, u32 hw_videoport)
                dispc_vp_write(_dispc, _vp, _idx, _reg);                \
        })
 
-#define OVR_REG_FLD_MOD(dispc, ovr, idx, val, start, end)              \
+#define OVR_REG_FLD_MOD(dispc, ovr, idx, val, mask)                    \
        ({                                                              \
                struct dispc_device *_dispc = (dispc);                  \
                u32 _ovr = (ovr);                                       \
                u32 _idx = (idx);                                       \
                u32 _reg = dispc_ovr_read(_dispc, _ovr, _idx);          \
-               FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val));    \
+               FIELD_MODIFY((mask), &_reg, (val));                     \
                dispc_ovr_write(_dispc, _ovr, _idx, _reg);              \
        })
 
@@ -1470,11 +1470,11 @@ static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc,
        u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
 
        OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
-                       hw_id, 4, 1);
-       OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
-                       x, 17, 6);
-       OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
-                       y, 30, 19);
+                       hw_id, GENMASK(4, 1));
+       OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), x,
+                       GENMASK(17, 6));
+       OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), y,
+                       GENMASK(30, 19));
 }
 
 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc,
@@ -1484,11 +1484,11 @@ static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc,
        u32 hw_id = dispc->feat->vid_info[hw_plane].hw_id;
 
        OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
-                       hw_id, 4, 1);
-       OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
-                       x, 13, 0);
-       OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
-                       y, 29, 16);
+                       hw_id, GENMASK(4, 1));
+       OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), x,
+                       GENMASK(13, 0));
+       OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), y,
+                       GENMASK(29, 16));
 }
 
 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
@@ -1523,7 +1523,7 @@ void dispc_ovr_enable_layer(struct dispc_device *dispc,
                return;
 
        OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
-                       !!enable, 0, 0);
+                       !!enable, GENMASK(0, 0));
 }
 
 /* CSC */