Xilinx: ARM: Renamed few legacy names as part of cleanup

Renamed few legacy names with valid zynq based names.
Removed ps7_init_hw header as it is not used.

Signed-off-by: Jagan <jaganna@xilinx.com>

diff --git a/arch/arm/include/asm/arch-zynq/xparameters.h b/arch/arm/include/asm/arch-zynq/xparameters.h
index ec4ea360c0a9d1556f9285b28911e7775d811200..451e979b931bae78e9c6024aa40a2884a025cb5e 100755 (executable)
--- a/arch/arm/include/asm/arch-zynq/xparameters.h
+++ b/arch/arm/include/asm/arch-zynq/xparameters.h
@@ -9,8 +9,7 @@
 #define XPAR_DDR2_SDRAM_MEM_BASEADDR   0x00000000
 #define XPAR_DDR2_SDRAM_MEM_HIGHADDR   0x00FFFFFF
 
-/* starting with PEEP8 designs, there is 256 MB of DDR */
-
+/* starting with Emulation8 designs, there is 256 MB of DDR */
 #define RTL_45
 #ifdef RTL_45
 #define XPAR_MEMORY_MB_SIZE            256

diff --git a/board/xilinx/zynq_common/lowlevel_init.S b/board/xilinx/zynq_common/lowlevel_init.S
index 441e6e235694998de6938db60bcb4fb7e042de5e..f0b1b5a99330ca5cccf4dc3b93299455a4031bc5 100755 (executable)
--- a/board/xilinx/zynq_common/lowlevel_init.S
+++ b/board/xilinx/zynq_common/lowlevel_init.S
@@ -1,7 +1,7 @@
 
 /*
- * This black box is a direct translation of init_ddrc.tcl. The Pele DDR controller
- * is initialized herein.
+ * This black box is a direct translation of init_ddrc.tcl.
+ * The Zynq DDR controller is initialized herein.
  * It needs lots of love and attention some day.
  */
 

diff --git a/board/xilinx/zynq_common/ps7_init_hw.h b/board/xilinx/zynq_common/ps7_init_hw.h
deleted file mode 100755 (executable)
index abef71c..0000000
--- a/board/xilinx/zynq_common/ps7_init_hw.h
+++ /dev/null
@@ -1,307 +0,0 @@
-#ifndef PS7_INIT_HW_H           /* prevent circular inclusions */\r
-#define PS7_INIT_HW_H           /* by using protection macros */\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-
-#define XPS_SYS_CTRL_BASEADDR          0xF8000000    
-\r
-#define SLCR_BASE_ADDRESS XPS_SYS_CTRL_BASEADDR\r
-\r
-/* MIO registers */\r
-#define SLCR_LOCK               (SLCR_BASE_ADDRESS + 0x4)\r
-#define SLCR_UNLOCK             (SLCR_BASE_ADDRESS + 0x8)\r
-#define SLCR_MIO0                      (SLCR_BASE_ADDRESS + 0x700)\r
-#define SLCR_MIO1                      (SLCR_BASE_ADDRESS + 0x704)\r
-#define SLCR_MIO2                      (SLCR_BASE_ADDRESS + 0x708)\r
-#define SLCR_MIO3                      (SLCR_BASE_ADDRESS + 0x70C)\r
-#define SLCR_MIO4                      (SLCR_BASE_ADDRESS + 0x710)\r
-#define SLCR_MIO5                      (SLCR_BASE_ADDRESS + 0x714)\r
-#define SLCR_MIO6                      (SLCR_BASE_ADDRESS + 0x718)\r
-#define SLCR_MIO7                      (SLCR_BASE_ADDRESS + 0x71C)\r
-#define SLCR_MIO8                      (SLCR_BASE_ADDRESS + 0x720)\r
-#define SLCR_MIO9                      (SLCR_BASE_ADDRESS + 0x724)\r
-#define SLCR_MIO10                     (SLCR_BASE_ADDRESS + 0x728)\r
-#define SLCR_MIO11                     (SLCR_BASE_ADDRESS + 0x72C)\r
-#define SLCR_MIO12                     (SLCR_BASE_ADDRESS + 0x730)\r
-#define SLCR_MIO13                     (SLCR_BASE_ADDRESS + 0x734)\r
-#define SLCR_MIO14                     (SLCR_BASE_ADDRESS + 0x738)\r
-#define SLCR_MIO15                     (SLCR_BASE_ADDRESS + 0x73C)\r
-#define SLCR_MIO16                     (SLCR_BASE_ADDRESS + 0x740)\r
-#define SLCR_MIO17                     (SLCR_BASE_ADDRESS + 0x744)\r
-#define SLCR_MIO18                     (SLCR_BASE_ADDRESS + 0x748)\r
-#define SLCR_MIO19                     (SLCR_BASE_ADDRESS + 0x74C)\r
-#define SLCR_MIO20                     (SLCR_BASE_ADDRESS + 0x750)\r
-#define SLCR_MIO21                     (SLCR_BASE_ADDRESS + 0x754)\r
-#define SLCR_MIO22                     (SLCR_BASE_ADDRESS + 0x758)\r
-#define SLCR_MIO23                     (SLCR_BASE_ADDRESS + 0x75C)\r
-#define SLCR_MIO24                     (SLCR_BASE_ADDRESS + 0x760)\r
-#define SLCR_MIO25                     (SLCR_BASE_ADDRESS + 0x764)\r
-#define SLCR_MIO26                     (SLCR_BASE_ADDRESS + 0x768)\r
-#define SLCR_MIO27                     (SLCR_BASE_ADDRESS + 0x76C)\r
-#define SLCR_MIO28                     (SLCR_BASE_ADDRESS + 0x770)\r
-#define SLCR_MIO29                     (SLCR_BASE_ADDRESS + 0x774)\r
-#define SLCR_MIO30                     (SLCR_BASE_ADDRESS + 0x778)\r
-#define SLCR_MIO31                     (SLCR_BASE_ADDRESS + 0x77C)\r
-#define SLCR_MIO32                     (SLCR_BASE_ADDRESS + 0x780)\r
-#define SLCR_MIO33                     (SLCR_BASE_ADDRESS + 0x784)\r
-#define SLCR_MIO34                     (SLCR_BASE_ADDRESS + 0x788)\r
-#define SLCR_MIO35                     (SLCR_BASE_ADDRESS + 0x78C)\r
-#define SLCR_MIO36                     (SLCR_BASE_ADDRESS + 0x790)\r
-#define SLCR_MIO37                     (SLCR_BASE_ADDRESS + 0x794)\r
-#define SLCR_MIO38                     (SLCR_BASE_ADDRESS + 0x798)\r
-#define SLCR_MIO39                     (SLCR_BASE_ADDRESS + 0x79C)\r
-#define SLCR_MIO40                     (SLCR_BASE_ADDRESS + 0x7A0)\r
-#define SLCR_MIO41                     (SLCR_BASE_ADDRESS + 0x7A4)\r
-#define SLCR_MIO42                     (SLCR_BASE_ADDRESS + 0x7A8)\r
-#define SLCR_MIO43                     (SLCR_BASE_ADDRESS + 0x7AC)\r
-#define SLCR_MIO44                     (SLCR_BASE_ADDRESS + 0x7B0)\r
-#define SLCR_MIO45                     (SLCR_BASE_ADDRESS + 0x7B4)\r
-#define SLCR_MIO46                     (SLCR_BASE_ADDRESS + 0x7B8)\r
-#define SLCR_MIO47                     (SLCR_BASE_ADDRESS + 0x7BC)\r
-#define SLCR_MIO48                     (SLCR_BASE_ADDRESS + 0x7C0)\r
-#define SLCR_MIO49                     (SLCR_BASE_ADDRESS + 0x7C4)\r
-#define SLCR_MIO50                     (SLCR_BASE_ADDRESS + 0x7C8)\r
-#define SLCR_MIO51                     (SLCR_BASE_ADDRESS + 0x7CC)\r
-#define SLCR_MIO52                     (SLCR_BASE_ADDRESS + 0x7D0)\r
-#define SLCR_MIO53                     (SLCR_BASE_ADDRESS + 0x7D4)\r
-#define SLCR_SDIO0_WP_CD               (SLCR_BASE_ADDRESS + 0x830)\r
-\r
-/* PLL registers */\r
-#define SLCR_ARM_PLL_CTRL              (SLCR_BASE_ADDRESS + 0x100) /* ARM PLL Control */\r
-#define SLCR_DDR_PLL_CTRL              (SLCR_BASE_ADDRESS + 0x104) /* DDR PLL Control */\r
-#define SLCR_IO_PLL_CTRL               (SLCR_BASE_ADDRESS + 0x108) /* IO PLL Control */\r
-#define SLCR_PLL_STATUS                        (SLCR_BASE_ADDRESS + 0x10C) /* PLL Status */\r
-#define SLCR_ARM_PLL_CFG               (SLCR_BASE_ADDRESS + 0x110) /* ARM PLL Configuration */\r
-#define SLCR_DDR_PLL_CFG               (SLCR_BASE_ADDRESS + 0x114) /* DDR PLL Configuration */\r
-#define SLCR_IO_PLL_CFG                (SLCR_BASE_ADDRESS + 0x118) /* IO PLL Configuration */\r
-#define SLCR_PLL_BG_CTRL               (SLCR_BASE_ADDRESS + 0x11C) /* PLL Bandgap control */\r
-#define SLCR_ARM_CLK_CTRL              (SLCR_BASE_ADDRESS + 0x120) /* CORTEX A9 Clock Control */\r
-#define SLCR_DDR_CLK_CTRL              (SLCR_BASE_ADDRESS + 0x124) /* DDR Clock Control */\r
-#define SLCR_DCI_CLK_CTRL              (SLCR_BASE_ADDRESS + 0x128) /* DCI clock control */\r
-#define SLCR_APER_CLK_CTRL             (SLCR_BASE_ADDRESS + 0x12C) /* AMBA Peripheral Clock Control */\r
-#define SLCR_USB0_CLK_CTRL             (SLCR_BASE_ADDRESS + 0x130) /* USB 0 ULPI Clock Control */\r
-#define SLCR_USB1_CLK_CTRL             (SLCR_BASE_ADDRESS + 0x134) /* USB 1 ULPI Clock Control */\r
-#define SLCR_GEM0_RCLK_CTRL            (SLCR_BASE_ADDRESS + 0x138) /* Gigabit Ethernet MAC 0 RX Clock Control */\r
-#define SLCR_GEM1_RCLK_CTRL            (SLCR_BASE_ADDRESS + 0x13C) /* Gigabit Ethernet MAC 0 RX Clock Control */\r
-#define SLCR_GEM0_CLK_CTRL             (SLCR_BASE_ADDRESS + 0x140) /* Gigabit Ethernet MAC 0 Ref Clock Control */\r
-#define SLCR_GEM1_CLK_CTRL             (SLCR_BASE_ADDRESS + 0x144) /* Gigabit Ethernet MAC 1 Ref Clock Control */\r
-#define SLCR_SMC_CLK_CTRL              (SLCR_BASE_ADDRESS + 0x148) /* SMC Reference Clock Control */\r
-#define SLCR_LQSPI_CLK_CTRL            (SLCR_BASE_ADDRESS + 0x14C) /* Linear Quad-SPI Reference Clock Control */\r
-#define SLCR_SDIO_CLK_CTRL             (SLCR_BASE_ADDRESS + 0x150) /* SDIO Reference Clock Control */\r
-#define SLCR_UART_CLK_CTRL             (SLCR_BASE_ADDRESS + 0x154) /* UART Reference Clock Control */\r
-#define SLCR_SPI_CLK_CTRL              (SLCR_BASE_ADDRESS + 0x158) /* SPI Reference Clock Control */\r
-#define SLCR_CAN_CLK_CTRL              (SLCR_BASE_ADDRESS + 0x15C) /* CAN Reference Clock Control */\r
-#define SLCR_CAN_MIO_CLK_CTRL  (SLCR_BASE_ADDRESS + 0x160) /* CAN MIO Clock Control */\r
-#define SLCR_DBG_CLK_CTRL      (SLCR_BASE_ADDRESS + 0x164) /* DBG Clock Control */\r
-#define SLCR_PCAP_CLK_CTRL     (SLCR_BASE_ADDRESS + 0x168) /* PCAP Clock Control */\r
-#define SLCR_TOPSW_CLK_CTRL    (SLCR_BASE_ADDRESS + 0x16C) /* TOPSW Clock Control */\r
-#define SLCR_FPGA0_CLK_CTRL    (SLCR_BASE_ADDRESS + 0x170) /* FPGA0 Clock Control */\r
-#define SLCR_FPGA1_CLK_CTRL    (SLCR_BASE_ADDRESS + 0x180) /* FPGA1 Clock Control */\r
-#define SLCR_FPGA2_CLK_CTRL    (SLCR_BASE_ADDRESS + 0x190) /* FPGA2 Clock Control */\r
-#define SLCR_FPGA3_CLK_CTRL    (SLCR_BASE_ADDRESS + 0x1A0) /* FPGA3 Clock Control */\r
-#define SLCR_PLL_PREDIVISOR            (SLCR_BASE_ADDRESS + 0x1C0) /* PLL pre devisor */\r
-#define SLCR_CLK_621_TRUE      (SLCR_BASE_ADDRESS + 0x1C4) /* CPU enable the 6:2:1 mode */\r
-\r
-/* MIO */\r
-#define MIO_LQSPI                      0x02\r
-#define        MIO_USB                         0x04\r
-#define        MIO_GEM                         0x02\r
-#define        MIO_UART                        0xE0\r
-#define        MIO_SPI                         0xA0\r
-#define        MIO_CAN                         0x20\r
-#define        MIO_I2C                         0x40\r
-#define MIO_SDIO                       0x80\r
-#define MIO_GPIO                       0x00\r
-#define MIO_MDIO0                      0x80\r
-#define MIO_MDIO1                      0xA0\r
-#define MIO_NAND                       0x10\r
-#define MIO_SRAM_NOR           0x08\r
-#define MIO_TTC                                0xC0\r
-#define MIO_WDT                                0x60\r
-#define MIO_MASK            0xFFF /* IOTYPE SPEED SEL TRI ENABLE Mask */\r
-#define SDIO0_CD_SEL_SHIFT     16\r
-\r
-#define TRI_ENABLE_IN                          (1 << 0)\r
-#define TRI_ENABLE_OUT                         (0 << 0)\r
-#define TRI_ENABLE_IN_OUT                      (0 << 0)\r
-#define SLOW_CMOS                                      (0 << 8)\r
-#define FAST_CMOS                                      (1 << 8)\r
-#define LVTTL                                          (0 << 9)\r
-#define LVCMOS18                                       (1 << 9)\r
-#define LVCMOS25                                       (2 << 9)\r
-#define LVCMOS33                                       (3 << 9)\r
-#define HSTL                                           (4 << 9)\r
-#define PULLUP_ENABLE                          (1 << 12)\r
-#define PULLUP_DISABLE                         (0 << 12)\r
-#define DISABLE_RCVR                           (1 << 13)\r
-\r
-/* PLL */\r
-#define PLL_RESET                                                      (1 << 0)\r
-#define PLL_PWRDWN                                                     (1 << 1)\r
-#define PLL_BYPASS_QUAL                                                (1 << 3)\r
-#define PLL_BYPASS_FORCE                                       (1 << 4)\r
-#define PLL_FDIV_SHIFT                                         12\r
-#define UPDATE_CLR                                                     (0 << 24)\r
-#define UPDATE_SERVICED                                                (1 << 25)\r
-\r
-#define PLL_RES_SHIFT                       4\r
-#define PLL_CP_SHIFT                        8\r
-#define PLL_LOCK_CNT_SHIFT                  12\r
-\r
-/* CPU */\r
-#define CPU_SRCSEL_SHIFT                                       4\r
-#define CPU_DIVISOR_SHIFT                                      8\r
-#define CPU_6OR4XCLKACT_ENABLE                         (1 << 24)\r
-#define CPU_3OR2XCLKACT_ENABLE                         (1 << 25)\r
-#define CPU_2XCLKACT_ENABLE                                    (1 << 26)\r
-#define        CPU_1XCLKACT_ENABLE                                     (1 << 27)\r
-#define        CPU_PERI_CLKACT_ENABLE                          (1 << 28)\r
-\r
-/* DDR */\r
-#define DDR_3XCLKACT_ENABLE                                    (1 << 0)\r
-#define DDR_2XCLKACT_ENABLE                                    (1 << 1)\r
-#define DDR_3XCLK_DIVISOR_SHIFT                                20\r
-#define DDR_2XCLK_DIVISOR_SHIFT                                26\r
-\r
-/* DCI */\r
-#define DCI_CLKACT_ENABLE                                      (1 << 0)\r
-#define DCI_DIVISOR0_SHIFT                                     8\r
-#define DCI_DIVISOR1_SHIFT                                     20\r
-\r
-/* APER */\r
-#define SLCR_DMA_CPU_2XCLKACT_ENABLE           (1 << 0)\r
-#define SLCR_USB0_CPU_1XCLKACT_ENABLE          (1 << 2)\r
-#define SLCR_USB1_CPU_1XCLKACT_ENABLE          (1 << 3)\r
-#define SLCR_GEM0_CPU_1XCLKACT_ENABLE          (1 << 6)\r
-#define SLCR_GEM1_CPU_1XCLKACT_ENABLE          (1 << 7)\r
-#define SLCR_SDI0_CPU_1XCLKACT_ENABLE          (1 << 10)\r
-#define SLCR_SDI1_CPU_1XCLKACT_ENABLE          (1 << 11)\r
-#define SLCR_SPI0_CPU_1XCLKACT_ENABLE          (1 << 14)\r
-#define SLCR_SPI1_CPU_1XCLKACT_ENABLE          (1 << 15)\r
-#define SLCR_CAN0_CPU_1XCLKACT_ENABLE          (1 << 16)\r
-#define SLCR_CAN1_CPU_1XCLKACT_ENABLE          (1 << 17)\r
-#define SLCR_I2C0_CPU_1XCLKACT_ENABLE          (1 << 18)\r
-#define SLCR_I2C1_CPU_1XCLKACT_ENABLE          (1 << 19)\r
-#define SLCR_UART0_CPU_1XCLKACT_ENABLE         (1 << 20)\r
-#define SLCR_UART1_CPU_1XCLKACT_ENABLE         (1 << 21)\r
-#define SLCR_GPIO_CPU_1XCLKACT_ENABLE          (1 << 22)\r
-#define SLCR_LQSPI_CPU_1XCLKACT_ENABLE         (1 << 23)\r
-#define SLCR_SMC_CPU_1XCLKACT_ENABLE           (1 << 24)\r
-\r
-/* PLL source */\r
-#define IO_PLL                 0x0\r
-#define ARM_PLL                        0x2\r
-#define DDR_PLL                        0x3\r
-\r
-/* CPU PLL source */\r
-#define CPU_ARM_PLL                    0x0\r
-#define CPU_DDR_PLL                    0x2\r
-#define CPU_IO_PLL                     0x3\r
-\r
-/* USB0 */\r
-#define USB0_CLKACT_ENABLE                                     (1 << 0)\r
-#define USB0_SRCSEL_SHIFT                                      4\r
-#define USB0_DIVISOR0_SHIFT                                    8\r
-#define USB0_DIVISOR1_SHIFT                                    20\r
-\r
-/* USB1 */\r
-#define USB1_CLKACT_ENABLE                                     (1 << 0)\r
-#define USB1_SRCSEL_SHIFT                                      4\r
-#define USB1_DIVISOR0_SHIFT                                    8\r
-#define USB1_DIVISOR1_SHIFT                                    20\r
-\r
-/* GEM0 RX */\r
-#define GEM0_RX_CLKACT_ENABLE                          (1 << 0)\r
-#define GEM0_RX_SRCSEL_SHIFT                           4\r
-#define GEM0_MIO_RX_CLK                     0\r
-#define GEM0_FMIO_RX_CLK                    1\r
-/* GEM1 RX */\r
-#define GEM1_RX_CLKACT_ENABLE                          (1 << 0)\r
-#define GEM1_RX_SRCSEL_SHIFT                           4\r
-#define GEM1_MIO_RX_CLK                     0\r
-#define GEM1_FMIO_RX_CLK                    1\r
-/* GEM0 */\r
-#define GEM0_CLKACT_ENABLE                                     (1 << 0)\r
-#define GEM0_SRCSEL_SHIFT                                      4\r
-#define GEM0_DIVISOR0_SHIFT                                    8\r
-#define GEM0_DIVISOR1_SHIFT                                    20\r
-\r
-/* GEM1 */\r
-#define GEM1_CLKACT_ENABLE                                     (1 << 0)\r
-#define GEM1_SRCSEL_SHIFT                                      4\r
-#define GEM1_DIVISOR0_SHIFT                                    8\r
-#define GEM1_DIVISOR1_SHIFT                                    20\r
-\r
-/* SMC */\r
-#define SMC_CLKACT_ENABLE                                      (1 << 0)\r
-#define SMC_SRCSEL_SHIFT                                       4\r
-#define SMC_DIVISOR_SHIFT                                      8\r
-\r
-/* LQSPI */\r
-#define LQSPI_CLKACT_ENABLE                                    (1 << 0)\r
-#define LQSPI_SRCSEL_SHIFT                                     4\r
-#define LQSPI_DIVISOR_SHIFT                                    8\r
-\r
-/* SDIO */\r
-#define SDIO0_CLKACT_ENABLE                                    (1 << 0)\r
-#define SDIO1_CLKACT_ENABLE                                    (1 << 1)\r
-#define SDIO_SRCSEL_SHIFT                                      4\r
-#define SDIO_DIVISOR_SHIFT                                     8\r
-\r
-/* UART */\r
-#define UART0_CLKACT_ENABLE                                    (1 << 0)\r
-#define UART1_CLKACT_ENABLE                                    (1 << 1)\r
-#define UART_SRCSEL_SHIFT                                      4\r
-#define UART_DIVISOR_SHIFT                                     8\r
-\r
-/* SPI */\r
-#define SPI0_CLKACT_ENABLE                                     (1 << 0)\r
-#define SPI1_CLKACT_ENABLE                                     (1 << 1)\r
-#define SPI_SRCSEL_SHIFT                                       4\r
-#define SPI_DIVISOR_SHIFT                                      8\r
-\r
-/* CAN */\r
-#define CAN0_CLKACT_ENABLE                                     (1 << 0)\r
-#define CAN1_CLKACT_ENABLE                                     (1 << 1)\r
-#define CAN_SRCSEL_SHIFT                                       4\r
-#define CAN_DIVISOR0_SHIFT                                     8\r
-#define CAN_DIVISOR1_SHIFT                                     20\r
-\r
-/* CAN MIO */\r
-#define CAN0_MUX\r
-#define CAN0_REF_SEL\r
-#define CAN1_MUX\r
-#define CAN1_REF_SEL\r
-\r
-/* FPGA */\r
-#define FPGA0_SRCSEL_SHIFT                                     4\r
-#define FPGA0_DIVISOR0_SHIFT                                   8\r
-#define FPGA0_DIVISOR1_SHIFT                                   20\r
-\r
-/* FPGA */\r
-#define FPGA1_SRCSEL_SHIFT                                     4\r
-#define FPGA1_DIVISOR0_SHIFT                                   8\r
-#define FPGA1_DIVISOR1_SHIFT                                   20\r
-\r
-/* FPGA */\r
-#define FPGA2_SRCSEL_SHIFT                                     4\r
-#define FPGA2_DIVISOR0_SHIFT                                   8\r
-#define FPGA2_DIVISOR1_SHIFT                                   20\r
-\r
-/* FPGA */\r
-#define FPGA3_SRCSEL_SHIFT                                     4\r
-#define FPGA3_DIVISOR0_SHIFT                                   8\r
-#define FPGA3_DIVISOR1_SHIFT                                   20\r
-\r
-/* PCAP */\r
-#define PCAP_CLKACT_ENABLE                                     (1 << 0)\r
-#define PCAP_SRCSEL_SHIFT                                      4\r
-#define PCAP_DIVISOR_SHIFT                                     8\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* end of protection macro */\r

diff --git a/drivers/mmc/zynq_mmc.c b/drivers/mmc/zynq_mmc.c
index 820acd26e43d2d02ab9eca0eb16624fb6aed6a7e..fc04026927e84702fc571356e0544f17c86bc648 100755 (executable)
--- a/drivers/mmc/zynq_mmc.c
+++ b/drivers/mmc/zynq_mmc.c
@@ -211,7 +211,7 @@ make_command (unsigned cmd)
        return retval;
 }
 
-static int pele_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
+static int zynq_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
                 struct mmc_data *data)
 {
        u32 status;
@@ -220,7 +220,7 @@ static int pele_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
        int result = 0;
 
 #ifdef DEBUG_VERBOSE
-       printf("pele_sdh_request: cmdidx: %d arg: 0x%x\n",
+       printf("zynq_sdh_request: cmdidx: %d arg: 0x%x\n",
            cmd->cmdidx, cmd->cmdarg);
 #endif
 
@@ -358,14 +358,14 @@ exit:
        return result;
 }
 
-static void pele_sdh_set_ios(struct mmc *mmc)
+static void zynq_sdh_set_ios(struct mmc *mmc)
 {
 #ifdef DEBUG
        printf("%s: voltages: 0x%x clock: 0x%x bus_width: 0x%x\n", __FUNCTION__,
                mmc->voltages, mmc->clock, mmc->bus_width);
 #endif
 }
-static int pele_sdh_init(struct mmc *mmc)
+static int zynq_sdh_init(struct mmc *mmc)
 {
        init_port();
        return 0;
@@ -385,9 +385,9 @@ int zynq_mmc_init(bd_t *bd)
                return -ENOMEM;
        }
        sprintf(mmc->name, "SDHCI");
-       mmc->send_cmd = pele_sdh_request;
-       mmc->set_ios = pele_sdh_set_ios;
-       mmc->init = pele_sdh_init;
+       mmc->send_cmd = zynq_sdh_request;
+       mmc->set_ios = zynq_sdh_set_ios;
+       mmc->init = zynq_sdh_init;
 
        mmc->host_caps = MMC_MODE_4BIT;
 

diff --git a/drivers/serial/serial_xpsuart.c b/drivers/serial/serial_xpsuart.c
index 51c94beb48c18fe47e41d0a97acc82d6556c9542..801b4a726994c255771ca945e486b30304365c8b 100644 (file)
--- a/drivers/serial/serial_xpsuart.c
+++ b/drivers/serial/serial_xpsuart.c
@@ -1,5 +1,5 @@
 /*
- * U-boot driver for Xilinx Dragonfire UART.
+ * Xilinx Zynq Serial PS driver
  * Based on existing U-boot serial drivers.
  */
 

diff --git a/drivers/serial/serial_xpsuart.h b/drivers/serial/serial_xpsuart.h
index 0c809c25bb1d9d90ecb4435849aab2ba1670e134..55d4d731e1cede1a25aced6918f1dcf6d8117507 100644 (file)
--- a/drivers/serial/serial_xpsuart.h
+++ b/drivers/serial/serial_xpsuart.h
@@ -1,7 +1,5 @@
 /*
- * Adapted from:
- * df_arm/trunk/ep3_1/sw/standalone/drivers/uart_v1_00_a/src/xuartepb_hw.h
- * as of svn rev 1377.
+ * Xilinx Zynq Serial PS driver, headers
  */
 
 #ifndef __XILINX_ZYNQ_UART_H__

diff --git a/drivers/spi/zynq_qspi_wrap.c b/drivers/spi/zynq_qspi_wrap.c
index bee9c7a2f545cd28f494383477202972cb961761..968bfa532a1ef391fe5ec52c20d32819a64fcbfd 100644 (file)
--- a/drivers/spi/zynq_qspi_wrap.c
+++ b/drivers/spi/zynq_qspi_wrap.c
@@ -14,12 +14,12 @@
 
 #include "zynq_qspi.h"
 
-struct pele_spi_slave {
+struct zynq_spi_slave {
        struct spi_slave  slave;
        struct spi_device qspi;
 };
 
-#define to_pele_spi_slave(s) container_of(s, struct pele_spi_slave, slave)
+#define to_zynq_spi_slave(s) container_of(s, struct zynq_spi_slave, slave)
 
 __attribute__((weak))
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
@@ -57,7 +57,7 @@ void spi_init()
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
                unsigned int max_hz, unsigned int mode)
 {
-       struct pele_spi_slave *pspi;
+       struct zynq_spi_slave *pspi;
 
 #ifdef DEBUG
        printf("spi_setup_slave: bus: %d cs: %d max_hz: %d mode: %d\n",
@@ -66,7 +66,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 
        xqspips_init_hw((void *)XPSS_QSPI_BASEADDR);
 
-       pspi = malloc(sizeof(struct pele_spi_slave));
+       pspi = malloc(sizeof(struct zynq_spi_slave));
        if (!pspi) {
                return NULL;
        }
@@ -87,13 +87,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 
 void spi_free_slave(struct spi_slave *slave)
 {
-       struct pele_spi_slave *pspi;
+       struct zynq_spi_slave *pspi;
 
 #ifdef DEBUG
        printf("spi_free_slave: slave: 0x%08x\n", (u32)slave);
 #endif
 
-       pspi = to_pele_spi_slave(slave);
+       pspi = to_zynq_spi_slave(slave);
        free(pspi);
 }
 
@@ -115,7 +115,7 @@ void spi_release_bus(struct spi_slave *slave)
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
                void *din, unsigned long flags)
 {
-       struct pele_spi_slave *pspi;
+       struct zynq_spi_slave *pspi;
        struct spi_transfer transfer;
 
 #ifdef DEBUG
@@ -123,7 +123,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
                (u32)slave, bitlen, (u32)dout, (u32)din, flags);
 #endif
 
-       pspi = (struct pele_spi_slave *)slave;
+       pspi = (struct zynq_spi_slave *)slave;
        transfer.tx_buf = dout;
        transfer.rx_buf = din;
        transfer.len = bitlen / 8;