return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
}
-static int vlv_hrawclk(struct intel_display *display)
-{
- /* RAWCLK_FREQ_VLV register updated from power well code */
- return vlv_get_cck_clock_hpll(display->drm, "hrawclk",
- CCK_DISPLAY_REF_CLOCK_CONTROL);
-}
-
static int i9xx_hrawclk(struct intel_display *display)
{
struct drm_i915_private *i915 = to_i915(display->drm);
else if (HAS_PCH_SPLIT(display))
freq = pch_rawclk(display);
else if (display->platform.valleyview || display->platform.cherryview)
- freq = vlv_hrawclk(display);
+ freq = vlv_clock_get_hrawclk(display->drm);
else if (DISPLAY_VER(display) >= 3)
freq = i9xx_hrawclk(display);
else
return hpll;
}
+int vlv_clock_get_hrawclk(struct drm_device *drm)
+{
+ /* RAWCLK_FREQ_VLV register updated from power well code */
+ return vlv_get_cck_clock_hpll(drm, "hrawclk", CCK_DISPLAY_REF_CLOCK_CONTROL);
+}
+
int vlv_clock_get_czclk(struct drm_device *drm)
{
struct drm_i915_private *i915 = to_i915(drm);
const char *name, u32 reg, int ref_freq);
int vlv_get_cck_clock_hpll(struct drm_device *drm,
const char *name, u32 reg);
+int vlv_clock_get_hrawclk(struct drm_device *drm);
int vlv_clock_get_czclk(struct drm_device *drm);
int vlv_clock_get_gpll(struct drm_device *drm);
bool intel_has_pending_fb_unpin(struct intel_display *display);