]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/i915: add vlv_clock_get_hrawclk()
authorJani Nikula <jani.nikula@intel.com>
Fri, 12 Sep 2025 14:48:44 +0000 (17:48 +0300)
committerJani Nikula <jani.nikula@intel.com>
Wed, 17 Sep 2025 08:29:06 +0000 (11:29 +0300)
Add vlv_clock_get_hrawclk() helper to hide the details from the callers.

Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://lore.kernel.org/r/ad3c3d0baf16eb0ef3a0ac3edfbab327c564e743.1757688216.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_cdclk.c
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_display.h

index 3025951eac2817a71415bede5482f080141a40c1..45ac378922ffc22f59c08fbc81897810ea85d9c4 100644 (file)
@@ -3561,13 +3561,6 @@ static int pch_rawclk(struct intel_display *display)
        return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 }
 
-static int vlv_hrawclk(struct intel_display *display)
-{
-       /* RAWCLK_FREQ_VLV register updated from power well code */
-       return vlv_get_cck_clock_hpll(display->drm, "hrawclk",
-                                     CCK_DISPLAY_REF_CLOCK_CONTROL);
-}
-
 static int i9xx_hrawclk(struct intel_display *display)
 {
        struct drm_i915_private *i915 = to_i915(display->drm);
@@ -3601,7 +3594,7 @@ u32 intel_read_rawclk(struct intel_display *display)
        else if (HAS_PCH_SPLIT(display))
                freq = pch_rawclk(display);
        else if (display->platform.valleyview || display->platform.cherryview)
-               freq = vlv_hrawclk(display);
+               freq = vlv_clock_get_hrawclk(display->drm);
        else if (DISPLAY_VER(display) >= 3)
                freq = i9xx_hrawclk(display);
        else
index eca9f2508e9da4562fc0f7ccee180acbcbed7b74..487870811d3a47c173dc1fea8d69616635facda9 100644 (file)
@@ -190,6 +190,12 @@ int vlv_get_cck_clock_hpll(struct drm_device *drm,
        return hpll;
 }
 
+int vlv_clock_get_hrawclk(struct drm_device *drm)
+{
+       /* RAWCLK_FREQ_VLV register updated from power well code */
+       return vlv_get_cck_clock_hpll(drm, "hrawclk", CCK_DISPLAY_REF_CLOCK_CONTROL);
+}
+
 int vlv_clock_get_czclk(struct drm_device *drm)
 {
        struct drm_i915_private *i915 = to_i915(drm);
index 811066a9e69d10d744f1d3529dcb3dd10dc64a63..dbfb4b4aee4e3582b10e3580031e6d0564ef76dc 100644 (file)
@@ -440,6 +440,7 @@ int vlv_get_cck_clock(struct drm_device *drm,
                      const char *name, u32 reg, int ref_freq);
 int vlv_get_cck_clock_hpll(struct drm_device *drm,
                           const char *name, u32 reg);
+int vlv_clock_get_hrawclk(struct drm_device *drm);
 int vlv_clock_get_czclk(struct drm_device *drm);
 int vlv_clock_get_gpll(struct drm_device *drm);
 bool intel_has_pending_fb_unpin(struct intel_display *display);