spi: spi-qpic-snand: handle 'use_ecc' parameter of qcom_spi_config_cw_read()

During raw read, neither the status of the ECC correction nor the erased
state of the codeword gets checked by the qcom_spi_read_cw_raw() function,
so in case of raw access reading the corresponding registers via DMA is
superfluous.

Extend the qcom_spi_config_cw_read() function to evaluate the existing
(but actually unused) 'use_ecc' parameter, and configure reading only
the flash status register when ECC is not used.

With the change, the code gets in line with the corresponding part of
the config_nand_cw_read() function in the qcom_nandc driver.

Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20250808-qpic-snand-handle-use_ecc-v1-1-67289fbb5e2f@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c
index 1f065d9907103f4e6bf09b8d14db2ecf312e6344..2812ffc421d27a7e932b8e11731bcbccd0d23600 100644 (file)
--- a/drivers/spi/spi-qpic-snand.c
+++ b/drivers/spi/spi-qpic-snand.c
@@ -491,9 +491,14 @@ qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int c
        qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
        qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
 
-       qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
-       qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
-                         NAND_BAM_NEXT_SGL);
+       if (use_ecc) {
+               qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
+               qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
+                                 NAND_BAM_NEXT_SGL);
+       } else {
+               qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1,
+                                 NAND_BAM_NEXT_SGL);
+       }
 }
 
 static int qcom_spi_block_erase(struct qcom_nand_controller *snandc)