--- /dev/null
+/*
+ * dts file for Xilinx ZynqMP ZCU100
+ *
+ * (C) Copyright 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Nathalie Chan King Choy <nathalie@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP ZCU100 RevA";
+ compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
+
+ aliases {
+ gpio0 = &gpio;
+ gpio1 = &max3107;
+ i2c0 = &i2c0;
+ rtc0 = &rtc;
+ serial0 = &uart1;
+ serial1 = &max3107;
+ serial2 = &dcc;
+ spi0 = &qspi;
+ spi1 = &spi0;
+ spi2 = &spi1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw4 {
+ label = "sw4";
+ gpios = <&gpio 39 GPIO_ACTIVE_LOW>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */
+ linux,code = <108>; /* down */
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ ds2 {
+ label = "ds2";
+ gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; /* uboot: gpio toggle 20 */
+ linux,default-trigger = "heartbeat";
+ };
+
+ ds3 {
+ label = "ds3";
+ gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx"; /* WLAN tx */
+ default-state = "off";
+ };
+
+ ds4 {
+ label = "ds4";
+ gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0rx"; /* WLAN rx */
+ default-state = "off";
+ };
+
+ ds5 {
+ label = "ds5";
+ gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* FIXME this is not correct - used fixed-regulator for it */
+ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */
+ label = "vbus_det";
+ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ clk3_6: clk3_6 { /* for spi uart max3107 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <3600000>;
+ };
+
+ ltc2952: ltc2952 { /* U7 */
+ compatible = "lltc,ltc2952";
+ trigger-gpios = <&gpio 23 GPIO_ACTIVE_LOW>; /* INT line - input */
+ watchdog-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; /* FIXME Bogus - set it up to max3107 */
+ kill-gpios = <&gpio 25 GPIO_ACTIVE_LOW>; /* KILL signal - output */
+ };
+
+ wmmcsdio_fixed: fixedregulator-mmcsdio {
+ compatible = "regulator-fixed";
+ regulator-name = "wmmcsdio_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sdio_pwrseq: sdio_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&max3107 1 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+ };
+
+ dp_clk_wiz: dp_clk_wiz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <267439000>;
+ clock-accuracy = <0x64>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+ i2cswitch@75 { /* u11 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2csw_0: i2c@0 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * LSEXP_I2C0
+ */
+ };
+ i2csw_1: i2c@1 { /* i2c mw 75 0 2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /*
+ * LSEXP_I2C1
+ */
+ };
+ i2csw_2: i2c@2 { /* i2c mw 75 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /*
+ * HSEXP_I2C2
+ */
+ };
+ i2csw_3: i2c@3 { /* i2c mw 75 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /*
+ * HSEXP_I2C3
+ */
+ };
+ i2csw_4: i2c@4 { /* i2c mw 75 0 10 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x5e>;
+
+ /* Also RTC, GPIO and regulators */
+ /*
+ CONFIG_GPIO_TPS6586X
+ CONFIG_MFD_TPS6586X
+ CONFIG_REGULATOR_TPS6586X
+ CONFIG_RTC_DRV_TPS6586X -- not sure about it
+ - max addr is 0xcd
+ */
+ /* rtc0 = "/i2c@7000d000/tps6586x@34"; */
+
+ /* also super fast mode 1M supported */
+
+ /* Comment it out because will be pre-programmed
+ at the factory */
+ /*
+ pmu: tps6586x@34 { // Custom TI PMIC u33
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupt-parent = <&gpio>;
+ interrupts = <39 GPIO_ACTIVE_LOW>; shared with gpio switch
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ ti,system-power-controller;
+
+ sys-supply = <&some_reg>;
+ // spec 12V
+
+ buck1 5V0
+ buck2 PSINTLP (no idea)
+ buck3 VCC_PSDDR 1V1
+ buck4 3V3
+ buck5 1V2
+ buck6 VCC_PSAUX 1V8
+
+
+
+ vin-sm0-supply = <&some_reg>;
+ vin-sm1-supply = <&some_reg>;
+ vin-sm2-supply = <&some_reg>;
+ vinldo01-supply = <...>;
+ vinldo23-supply = <...>;
+ vinldo4-supply = <...>;
+ vinldo678-supply = <...>;
+ vinldo9-supply = <...>;
+
+ regulators {
+ sys_reg: sys {
+ regulator-name = "vdd_sys";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sm0_reg: sm0 {
+ regulator-min-microvolt = < 725000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sm1_reg: sm1 {
+ regulator-min-microvolt = < 725000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sm2_reg: sm2 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <4550000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo0_reg: ldo0 {
+ regulator-name = "PCIE CLK";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo1_reg: ldo1 {
+ regulator-min-microvolt = < 725000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-min-microvolt = < 725000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ ldo3_reg: ldo3 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo4_reg: ldo4 {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <2475000>;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo9_reg: ldo9 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ // FIXME look at this one
+ ldo_rtc {
+ regulator-name = "vdd_rtc_out,vdd_cell";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+ */
+
+ };
+ i2csw_5: i2c@5 { /* i2c mw 75 0 20 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /*
+ * SYSMON
+ */
+ };
+ i2csw_6: i2c@6 { /* i2c mw 75 0 40 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /*
+ * EEPROM with globally unique ID (will provide MAC address)
+ */
+ eeprom@50 { /* u35 - 24aa02E48T */
+ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */
+ reg = <0x50>; /* low 3 bits: don't care */
+ };
+ };
+ i2csw_7: i2c@7 { /* i2c mw 75 0 80 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /*
+ * usb5744 - U5
+ * 100kHz - this is default freq for us
+ */
+ /* FIXME 0x2c 0x2d - disabled because of SMBUS */
+ };
+ };
+};
+
+&qspi {
+ status = "okay"; /* This device may be DNP for cost savings */
+ flash@0 { /* single x4 - 16 MB flash at U13 */
+ compatible = "n25q128a13", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ partition@qspi-fsbl-uboot { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x9E0000>;
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+/* SD0 only supports 3.3V, no level shifter */
+&sdhci0 {
+ status = "okay";
+ no-1-8-v;
+ broken-cd; /* CD has to be enabled by default */
+ disable-wp;
+ xlnx,mio_bank = <0>;
+};
+
+&sdhci1 {
+ status = "okay";
+ bus-width = <0x4>;
+ xlnx,mio_bank = <0>;
+ non-removable;
+ disable-wp;
+ cap-power-off-card;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ max-frequency = <16000000>;
+ vqmmc-supply = <&wmmcsdio_fixed>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1831";
+ reg = <2>;
+ interrupt-parent = <&gpio>;
+ interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
+ };
+};
+
+&serdes {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ max3107: max3107@0 { /* I'm assuming no offset...? */
+ compatible = "maxim,max3107";
+ spi-max-frequency = <26000000>;
+ reg = <0>;
+ interrupt-parent = <&gpio>;
+ interrupts = <77 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk3_6>;
+ clock-names = "osc";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&spi1 { /* High Speed connector */
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "peripheral";
+/* phy-names = "usb3-phy";
+ phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+};
+
+&dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+/* phy-names = "usb3-phy";
+ phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */
+};
+
+&xilinx_drm {
+ status = "okay";
+ clocks = <&dp_clk_wiz>;
+};
+
+&xlnx_dp {
+ status = "okay";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&lane1 PHY_TYPE_DP 0 1 27000000>,
+ <&lane0 PHY_TYPE_DP 1 1 27000000>;
+};
+
+&xlnx_dp_sub {
+ status = "okay";
+};
+
+&xlnx_dp_snd_pcm0 {
+ status = "okay";
+};
+
+&xlnx_dp_snd_pcm1 {
+ status = "okay";
+};
+
+&xlnx_dp_snd_card {
+ status = "okay";
+};
+
+&xlnx_dp_snd_codec0 {
+ status = "okay";
+};
+
+&xlnx_dpdma {
+ status = "okay";
+};
/*
- * dts file for Xilinx ZynqMP ZCU100
+ * dts file for Xilinx ZynqMP ZCU100 revB
*
* (C) Copyright 2016, Xilinx, Inc.
*
#include <dt-bindings/phy/phy.h>
/ {
- model = "ZynqMP ZCU100 RevA";
- compatible = "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
+ model = "ZynqMP ZCU100 RevB";
+ compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
aliases {
gpio0 = &gpio;
- gpio1 = &max3107;
i2c0 = &i2c0;
rtc0 = &rtc;
serial0 = &uart1;
- serial1 = &max3107;
- serial2 = &dcc;
- spi0 = &qspi;
- spi1 = &spi0;
- spi2 = &spi1;
+ serial1 = &dcc;
+ spi0 = &spi0;
+ spi1 = &spi1;
usb0 = &usb0;
usb1 = &usb1;
mmc0 = &sdhci0;
autorepeat;
sw4 {
label = "sw4";
- gpios = <&gpio 39 GPIO_ACTIVE_LOW>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */
+ gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
linux,code = <108>; /* down */
- gpio-key,wakeup;
+ gpio-key,wakeup; /* FIXME test this */
autorepeat;
};
};
};
/* FIXME this is not correct - used fixed-regulator for it */
- vbus_det { /* U5 USB5744 VBUS detection via MIO7 */
+ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
label = "vbus_det";
- gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
- clk3_6: clk3_6 { /* for spi uart max3107 */
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <3600000>;
- };
-
ltc2952: ltc2952 { /* U7 */
- compatible = "lltc,ltc2952";
- trigger-gpios = <&gpio 23 GPIO_ACTIVE_LOW>; /* INT line - input */
- watchdog-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; /* FIXME Bogus - set it up to max3107 */
- kill-gpios = <&gpio 25 GPIO_ACTIVE_LOW>; /* KILL signal - output */
+ /*
+ * FIXME this is ltc2954 not ltc2952 - try this driver and
+ * maybe just extend compatible string.
+ */
+ compatible = "lltc,ltc2954", "lltc,ltc2952";
+ trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */
+ /* If there is HW watchdog on mezzanine this signal should be connected there */
+ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* FIXME - unconnected MIO pin now */
+ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */
};
wmmcsdio_fixed: fixedregulator-mmcsdio {
sdio_pwrseq: sdio_pwrseq {
compatible = "mmc-pwrseq-simple";
- reset-gpios = <&max3107 1 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+ reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
};
+ /* FIXME - not tested */
dp_clk_wiz: dp_clk_wiz {
compatible = "fixed-clock";
#clock-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
- /*
- * SYSMON
- */
+ /* PS_PMBUS */
+ ina226@40 { /* u35 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <10000>;
+ /* MIO31 is alert which should be routed to PMUFW */
+ };
+
+
+
};
i2csw_6: i2c@6 { /* i2c mw 75 0 40 */
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
/*
- * EEPROM with globally unique ID (will provide MAC address)
+ * Not Connected
*/
- eeprom@50 { /* u35 - 24aa02E48T */
- compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */
- reg = <0x50>; /* low 3 bits: don't care */
- };
};
i2csw_7: i2c@7 { /* i2c mw 75 0 80 */
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
/*
- * usb5744 - U5
+ * usb5744 (DNP) - U5
* 100kHz - this is default freq for us
*/
- /* FIXME 0x2c 0x2d - disabled because of SMBUS */
- };
- };
-};
-
-&qspi {
- status = "okay"; /* This device may be DNP for cost savings */
- flash@0 { /* single x4 - 16 MB flash at U13 */
- compatible = "n25q128a13", "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@qspi-fsbl-uboot { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@qspi-linux { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@qspi-device-tree { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@qspi-rootfs { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x9E0000>;
};
};
};
status = "okay";
};
-&spi0 {
+&spi0 { /* Low Speed connector */
status = "okay";
- max3107: max3107@0 { /* I'm assuming no offset...? */
- compatible = "maxim,max3107";
- spi-max-frequency = <26000000>;
- reg = <0>;
- interrupt-parent = <&gpio>;
- interrupts = <77 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&clk3_6>;
- clock-names = "osc";
- gpio-controller;
- #gpio-cells = <2>;
- };
};
&spi1 { /* High Speed connector */
projects / thirdparty / u-boot.git / commitdiff
