arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC

Add UFS host controller and PHY nodes for x1e80100 SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260211132926.3716716-3-pradeep.pragallapati@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index 40843b164bfacbde814c706aede87bb2efe6dac9..5bf830aafc5aca03591507265b2063054df79a5a 100644 (file)
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -847,9 +847,9 @@
                                 <0>,
                                 <0>,
                                 <0>,
-                                <0>,
-                                <0>,
-                                <0>;
+                                <&ufs_mem_phy 0>,
+                                <&ufs_mem_phy 1>,
+                                <&ufs_mem_phy 2>;
 
                        power-domains = <&rpmhpd RPMHPD_CX>;
                        #clock-cells = <1>;
@@ -3881,6 +3881,122 @@
                        status = "disabled";
                };
 
+               ufs_mem_phy: phy@1d80000 {
+                       compatible = "qcom,x1e80100-qmp-ufs-phy",
+                                    "qcom,sm8550-qmp-ufs-phy";
+                       reg = <0x0 0x01d80000 0x0 0x2000>;
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+                                <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
+
+                       clock-names = "ref",
+                                     "ref_aux",
+                                     "qref";
+                       resets = <&ufs_mem_hc 0>;
+                       reset-names = "ufsphy";
+
+                       power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
+
+                       #clock-cells = <1>;
+                       #phy-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               ufs_mem_hc: ufshc@1d84000 {
+                       compatible = "qcom,x1e80100-ufshc",
+                                    "qcom,sm8550-ufshc",
+                                    "qcom,ufshc";
+                       reg = <0x0 0x01d84000 0x0 0x3000>;
+
+                       interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+                       clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+                                <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+                                <&gcc GCC_UFS_PHY_AHB_CLK>,
+                                <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+                                <&rpmhcc RPMH_LN_BB_CLK3>,
+                                <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+                                <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+                                <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+                       clock-names = "core_clk",
+                                     "bus_aggr_clk",
+                                     "iface_clk",
+                                     "core_clk_unipro",
+                                     "ref_clk",
+                                     "tx_lane0_sync_clk",
+                                     "rx_lane0_sync_clk",
+                                     "rx_lane1_sync_clk";
+
+                       operating-points-v2 = <&ufs_opp_table>;
+
+                       resets = <&gcc GCC_UFS_PHY_BCR>;
+                       reset-names = "rst";
+
+                       interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                                       <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       interconnect-names = "ufs-ddr",
+                                            "cpu-ufs";
+
+                       power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+                       required-opps = <&rpmhpd_opp_nom>;
+
+                       iommus = <&apps_smmu 0x1a0 0>;
+                       dma-coherent;
+
+                       lanes-per-direction = <2>;
+
+                       phys = <&ufs_mem_phy>;
+                       phy-names = "ufsphy";
+
+                       #reset-cells = <1>;
+
+                       status = "disabled";
+
+                       ufs_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-75000000 {
+                                       opp-hz = /bits/ 64 <75000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <75000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                               };
+
+                               opp-150000000 {
+                                       opp-hz = /bits/ 64 <150000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <150000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>;
+                                       required-opps = <&rpmhpd_opp_svs>;
+                               };
+
+                               opp-300000000 {
+                                       opp-hz = /bits/ 64 <300000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <300000000>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>,
+                                                /bits/ 64 <0>;
+                                       required-opps = <&rpmhpd_opp_nom>;
+                               };
+                       };
+               };
+
                cryptobam: dma-controller@1dc4000 {
                        compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
                        reg = <0x0 0x01dc4000 0x0 0x28000>;