PR target/11607 and PR target/11516

	PR target/11607 and PR target/11516
	* pa.md (extzv, extv, insv): Revert latter half of last patch.

From-SVN: r69707

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 74f3eea3844a0b7ff634f8641112e5683df84603..5c393a878aec7ceaab25f97621552f3c2f2f715e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2003-07-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+       PR target/11607 and PR target/11516
+       * pa.md (extzv, extv, insv): Revert latter half of last patch.
+
 2003-07-22  Mark Mitchell  <mark@codesourcery.com>
 
        * fold-const.c (force_fit_type): Handle OFFSET_TYPE.

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 35369966d59b382e9aa9b779e74b598f6149f3cd..053775687e560279acc967e6917cb7b4f265a265 100644 (file)
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -7158,17 +7158,12 @@
     FAIL;
 
   if (TARGET_64BIT)
-    {
-      if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 64
-          || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 63)
-       FAIL;
-      emit_insn (gen_extzv_64 (operands[0], operands[1],
-                              operands[2], operands[3]));
-    }
+    emit_insn (gen_extzv_64 (operands[0], operands[1],
+                            operands[2], operands[3]));
   else
     {
-      if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 32
-          || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 31)
+      if (! uint5_operand (operands[2], SImode)
+         || ! uint5_operand (operands[3], SImode))
        FAIL;
       emit_insn (gen_extzv_32 (operands[0], operands[1],
                               operands[2], operands[3]));
@@ -7179,8 +7174,8 @@
 (define_insn "extzv_32"
   [(set (match_operand:SI 0 "register_operand" "=r")
        (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-                        (match_operand:SI 2 "uint32_operand" "")
-                        (match_operand:SI 3 "uint32_operand" "")))]
+                        (match_operand:SI 2 "uint5_operand" "")
+                        (match_operand:SI 3 "uint5_operand" "")))]
   ""
   "{extru|extrw,u} %1,%3+%2-1,%2,%0"
   [(set_attr "type" "shift")
@@ -7229,17 +7224,12 @@
     FAIL;
 
   if (TARGET_64BIT)
-    {
-      if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 64
-          || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 63)
-       FAIL;
-      emit_insn (gen_extv_64 (operands[0], operands[1],
-                             operands[2], operands[3]));
-    }
+    emit_insn (gen_extv_64 (operands[0], operands[1],
+                           operands[2], operands[3]));
   else
     {
-      if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 32
-          || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 31)
+      if (! uint5_operand (operands[2], SImode)
+         || ! uint5_operand (operands[3], SImode))
        FAIL;
       emit_insn (gen_extv_32 (operands[0], operands[1],
                              operands[2], operands[3]));
@@ -7250,8 +7240,8 @@
 (define_insn "extv_32"
   [(set (match_operand:SI 0 "register_operand" "=r")
        (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
-                        (match_operand:SI 2 "uint32_operand" "")
-                        (match_operand:SI 3 "uint32_operand" "")))]
+                        (match_operand:SI 2 "uint5_operand" "")
+                        (match_operand:SI 3 "uint5_operand" "")))]
   ""
   "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
   [(set_attr "type" "shift")
@@ -7297,17 +7287,12 @@
   "
 {
   if (TARGET_64BIT)
-    {
-      if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 64
-          || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 63)
-       FAIL;
-      emit_insn (gen_insv_64 (operands[0], operands[1],
-                             operands[2], operands[3]));
-    }
+    emit_insn (gen_insv_64 (operands[0], operands[1],
+                           operands[2], operands[3]));
   else
     {
-      if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 32
-          || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 31)
+      if (! uint5_operand (operands[2], SImode)
+         || ! uint5_operand (operands[3], SImode))
        FAIL;
       emit_insn (gen_insv_32 (operands[0], operands[1],
                              operands[2], operands[3]));
@@ -7317,8 +7302,8 @@
 
 (define_insn "insv_32"
   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
-                        (match_operand:SI 1 "uint32_operand" "")
-                        (match_operand:SI 2 "uint32_operand" ""))
+                        (match_operand:SI 1 "uint5_operand" "")
+                        (match_operand:SI 2 "uint5_operand" ""))
        (match_operand:SI 3 "arith5_operand" "r,L"))]
   ""
   "@