[AArch64] Model CSEL instruction in Cortex-A57 scheduling model

	* config/arm/cortex-a57.md (cortex_a57_alu):
	Handle csel type.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@237249 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 89c9f766cce988e287df45b6525d539144b35b2c..da572a41a7d4acf4003e7d0827b7d86286e8e7bd 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2016-06-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/arm/cortex-a57.md (cortex_a57_alu):
+       Handle csel type.
+
 2016-06-08  Martin Sebor  <msebor@redhat.com>
            Jakub Jelinek  <jakub@redhat.com>
 

diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md
index 37912db464315a0d70835b81991e8e07a4d9db89..c8cf80f4ba7ed99b46c920c2d0ad3299050ec473 100644 (file)
--- a/gcc/config/arm/cortex-a57.md
+++ b/gcc/config/arm/cortex-a57.md
@@ -297,7 +297,7 @@
        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
                        alu_sreg,alus_sreg,logic_reg,logics_reg,\
                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
-                       adr,bfm,clz,rbit,rev,alu_dsp_reg,\
+                       adr,bfm,clz,csel,rbit,rev,alu_dsp_reg,\
                        rotate_imm,shift_imm,shift_reg,\
                        mov_imm,mov_reg,\
                        mvn_imm,mvn_reg,\