#define POLL_INTERVAL_US 10
+#define BTINTEL_PCIE_DMA_ALIGN_128B 128 /* 128 byte aligned */
+
/* Intel Bluetooth PCIe device id table */
static const struct pci_device_id btintel_pcie_table[] = {
/* BlazarI, Wildcat Lake */
return 0;
}
-static void btintel_pcie_setup_ia(struct btintel_pcie_data *data,
- dma_addr_t p_addr, void *v_addr,
- struct ia *ia)
-{
- /* TR Head Index Array */
- ia->tr_hia_p_addr = p_addr;
- ia->tr_hia = v_addr;
-
- /* TR Tail Index Array */
- ia->tr_tia_p_addr = p_addr + sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES;
- ia->tr_tia = v_addr + sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES;
-
- /* CR Head index Array */
- ia->cr_hia_p_addr = p_addr + (sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES * 2);
- ia->cr_hia = v_addr + (sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES * 2);
-
- /* CR Tail Index Array */
- ia->cr_tia_p_addr = p_addr + (sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES * 3);
- ia->cr_tia = v_addr + (sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES * 3);
-}
-
static void btintel_pcie_free(struct btintel_pcie_data *data)
{
btintel_pcie_free_rxq_bufs(data, &data->rxq);
size_t total;
dma_addr_t p_addr;
void *v_addr;
+ size_t tfd_size, frbd_size, ctx_size, ci_size, urbd0_size, urbd1_size;
/* Allocate the chunk of DMA memory for descriptors, index array, and
* context information, instead of allocating individually.
* The DMA memory for data buffer is allocated while setting up the
* each queue.
*
- * Total size is sum of the following
+ * Total size is sum of the following and each of the individual sizes
+ * are aligned to 128 bytes before adding up.
+ *
* + size of TFD * Number of descriptors in queue
* + size of URBD0 * Number of descriptors in queue
* + size of FRBD * Number of descriptors in queue
* + size of index * Number of queues(2) * type of index array(4)
* + size of context information
*/
- total = (sizeof(struct tfd) + sizeof(struct urbd0)) * BTINTEL_PCIE_TX_DESCS_COUNT;
- total += (sizeof(struct frbd) + sizeof(struct urbd1)) * BTINTEL_PCIE_RX_DESCS_COUNT;
+ tfd_size = ALIGN(sizeof(struct tfd) * BTINTEL_PCIE_TX_DESCS_COUNT,
+ BTINTEL_PCIE_DMA_ALIGN_128B);
+ urbd0_size = ALIGN(sizeof(struct urbd0) * BTINTEL_PCIE_TX_DESCS_COUNT,
+ BTINTEL_PCIE_DMA_ALIGN_128B);
- /* Add the sum of size of index array and size of ci struct */
- total += (sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES * 4) + sizeof(struct ctx_info);
+ frbd_size = ALIGN(sizeof(struct frbd) * BTINTEL_PCIE_RX_DESCS_COUNT,
+ BTINTEL_PCIE_DMA_ALIGN_128B);
+ urbd1_size = ALIGN(sizeof(struct urbd1) * BTINTEL_PCIE_RX_DESCS_COUNT,
+ BTINTEL_PCIE_DMA_ALIGN_128B);
+
+ ci_size = ALIGN(sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES,
+ BTINTEL_PCIE_DMA_ALIGN_128B);
+
+ ctx_size = ALIGN(sizeof(struct ctx_info), BTINTEL_PCIE_DMA_ALIGN_128B);
+
+ total = tfd_size + urbd0_size + frbd_size + urbd1_size + ctx_size + ci_size * 4;
- /* Allocate DMA Pool */
data->dma_pool = dma_pool_create(KBUILD_MODNAME, &data->pdev->dev,
- total, BTINTEL_PCIE_DMA_POOL_ALIGNMENT, 0);
+ total, BTINTEL_PCIE_DMA_ALIGN_128B, 0);
if (!data->dma_pool) {
err = -ENOMEM;
goto exit_error;
data->txq.tfds_p_addr = p_addr;
data->txq.tfds = v_addr;
- p_addr += (sizeof(struct tfd) * BTINTEL_PCIE_TX_DESCS_COUNT);
- v_addr += (sizeof(struct tfd) * BTINTEL_PCIE_TX_DESCS_COUNT);
+ p_addr += tfd_size;
+ v_addr += tfd_size;
/* Setup urbd0 */
data->txq.urbd0s_p_addr = p_addr;
data->txq.urbd0s = v_addr;
- p_addr += (sizeof(struct urbd0) * BTINTEL_PCIE_TX_DESCS_COUNT);
- v_addr += (sizeof(struct urbd0) * BTINTEL_PCIE_TX_DESCS_COUNT);
+ p_addr += urbd0_size;
+ v_addr += urbd0_size;
/* Setup FRBD*/
data->rxq.frbds_p_addr = p_addr;
data->rxq.frbds = v_addr;
- p_addr += (sizeof(struct frbd) * BTINTEL_PCIE_RX_DESCS_COUNT);
- v_addr += (sizeof(struct frbd) * BTINTEL_PCIE_RX_DESCS_COUNT);
+ p_addr += frbd_size;
+ v_addr += frbd_size;
/* Setup urbd1 */
data->rxq.urbd1s_p_addr = p_addr;
data->rxq.urbd1s = v_addr;
- p_addr += (sizeof(struct urbd1) * BTINTEL_PCIE_RX_DESCS_COUNT);
- v_addr += (sizeof(struct urbd1) * BTINTEL_PCIE_RX_DESCS_COUNT);
+ p_addr += urbd1_size;
+ v_addr += urbd1_size;
/* Setup data buffers for txq */
err = btintel_pcie_setup_txq_bufs(data, &data->txq);
if (err)
goto exit_error_txq;
- /* Setup Index Array */
- btintel_pcie_setup_ia(data, p_addr, v_addr, &data->ia);
+ /* TR Head Index Array */
+ data->ia.tr_hia_p_addr = p_addr;
+ data->ia.tr_hia = v_addr;
+ p_addr += ci_size;
+ v_addr += ci_size;
+
+ /* TR Tail Index Array */
+ data->ia.tr_tia_p_addr = p_addr;
+ data->ia.tr_tia = v_addr;
+ p_addr += ci_size;
+ v_addr += ci_size;
+
+ /* CR Head index Array */
+ data->ia.cr_hia_p_addr = p_addr;
+ data->ia.cr_hia = v_addr;
+ p_addr += ci_size;
+ v_addr += ci_size;
+
+ /* CR Tail Index Array */
+ data->ia.cr_tia_p_addr = p_addr;
+ data->ia.cr_tia = v_addr;
+ p_addr += ci_size;
+ v_addr += ci_size;
/* Setup data buffers for dbgc */
err = btintel_pcie_setup_dbgc(data);
goto exit_error_txq;
/* Setup Context Information */
- p_addr += sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES * 4;
- v_addr += sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES * 4;
-
data->ci = v_addr;
data->ci_p_addr = p_addr;