5.0-stable patches

added patches:
	platform-x86-intel_pmc_core-fix-pch-ip-name.patch
	platform-x86-intel_pmc_core-handle-cfl-regmap-properly.patch

diff --git a/queue-5.0/platform-x86-intel_pmc_core-fix-pch-ip-name.patch b/queue-5.0/platform-x86-intel_pmc_core-fix-pch-ip-name.patch
new file mode 100644 (file)
index 0000000..69b9984
--- /dev/null
+++ b/queue-5.0/platform-x86-intel_pmc_core-fix-pch-ip-name.patch
@@ -0,0 +1,35 @@
+From d6827015e671cd17871c9b7a0fabe06c044f7470 Mon Sep 17 00:00:00 2001
+From: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
+Date: Fri, 1 Feb 2019 13:02:27 +0530
+Subject: platform/x86: intel_pmc_core: Fix PCH IP name
+
+From: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
+
+commit d6827015e671cd17871c9b7a0fabe06c044f7470 upstream.
+
+For Cannonlake and Icelake, the IP name for Res_6 should be SPF i.e.
+South Port F. No functional change is intended other than just renaming
+the IP appropriately.
+
+Cc: "David E. Box" <david.e.box@intel.com>
+Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
+Fixes: 291101f6a735 ("platform/x86: intel_pmc_core: Add CannonLake PCH support")
+Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/platform/x86/intel_pmc_core.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/platform/x86/intel_pmc_core.c
++++ b/drivers/platform/x86/intel_pmc_core.c
+@@ -205,7 +205,7 @@ static const struct pmc_bit_map cnp_pfea
+       {"CNVI",                BIT(3)},
+       {"UFS0",                BIT(4)},
+       {"EMMC",                BIT(5)},
+-      {"Res_6",               BIT(6)},
++      {"SPF",                 BIT(6)},
+       {"SBR6",                BIT(7)},
+ 
+       {"SBR7",                BIT(0)},

diff --git a/queue-5.0/platform-x86-intel_pmc_core-handle-cfl-regmap-properly.patch b/queue-5.0/platform-x86-intel_pmc_core-handle-cfl-regmap-properly.patch
new file mode 100644 (file)
index 0000000..8cb194a
--- /dev/null
+++ b/queue-5.0/platform-x86-intel_pmc_core-handle-cfl-regmap-properly.patch
@@ -0,0 +1,38 @@
+From e50af8332785355de3cb40d9f5e8c45dbfc86f53 Mon Sep 17 00:00:00 2001
+From: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
+Date: Fri, 1 Feb 2019 13:02:25 +0530
+Subject: platform/x86: intel_pmc_core: Handle CFL regmap properly
+
+From: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
+
+commit e50af8332785355de3cb40d9f5e8c45dbfc86f53 upstream.
+
+Only Coffeelake should use Cannonlake regmap other than Cannonlake
+platform. This allows Coffeelake special handling only when there is no
+matching PCI device and default reg map selected as per CPUID is for
+Sunrisepoint PCH. This change is needed to enable support for newer SoCs
+such as Icelake.
+
+Cc: "David E. Box" <david.e.box@intel.com>
+Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
+Fixes: 661405bd817b ("platform/x86: intel_pmc_core: Special case for Coffeelake")
+Acked-by: "David E. Box" <david.e.box@linux.intel.com>
+Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/platform/x86/intel_pmc_core.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/platform/x86/intel_pmc_core.c
++++ b/drivers/platform/x86/intel_pmc_core.c
+@@ -802,7 +802,7 @@ static int __init pmc_core_probe(void)
+        * Sunrisepoint PCH regmap can't be used. Use Cannonlake PCH regmap
+        * in this case.
+        */
+-      if (!pci_dev_present(pmc_pci_ids))
++      if (pmcdev->map == &spt_reg_map && !pci_dev_present(pmc_pci_ids))
+               pmcdev->map = &cnp_reg_map;
+ 
+       if (lpit_read_residency_count_address(&slp_s0_addr))

diff --git a/queue-5.0/series b/queue-5.0/series
index 27c46d9c5abe2c5f1c998b83d529da5024eef7e3..a16722b5d01713eeb44b258a1a74dad1fc4a0c3f 100644 (file)
--- a/queue-5.0/series
+++ b/queue-5.0/series
@@ -101,3 +101,5 @@ kvm-vmx-save-rsi-to-an-unused-output-in-the-vcpu-run-asm-blob.patch
 kvm-nvmx-remove-a-rogue-rax-clobber-from-nested_vmx_check_vmentry_hw.patch
 kvm-vmx-fix-typos-in-vmentry-vmexit-control-setting.patch
 kvm-lapic-check-for-in-kernel-lapic-before-deferencing-apic-pointer.patch
+platform-x86-intel_pmc_core-fix-pch-ip-name.patch
+platform-x86-intel_pmc_core-handle-cfl-regmap-properly.patch