memory: tegra: Prepare for supporting multiple intmask registers

Add a new structure for the intmask register e.g. MC_INTMASK_0 and
it's mask value. Add an array of these new structures to prepare for
supporting multiple intmask registers. This is done in preparation for
adding support for Tegra264 which supports multiple intmask registers.

Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260226163115.1152181-6-ketanp@nvidia.com
[krzk: Fix checkpatch warning]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 5d0d9b7fc53490db441bb20b012a0ddb61edf586..dccebbed78339f7dc0f5368ace1fb516dad7c766 100644 (file)
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -586,9 +586,9 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
                }
 
                /* mask all interrupts to avoid flooding */
-               status = mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmask;
+               status = mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmasks[0].mask;
        } else {
-               status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
+               status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmasks[0].mask;
        }
 
        if (!status)
@@ -969,11 +969,13 @@ static int tegra_mc_probe(struct platform_device *pdev)
                        }
                }
 
-               if (mc->soc->num_channels)
-                       mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask,
-                                    MC_INTMASK);
-               else
-                       mc_writel(mc, mc->soc->intmask, MC_INTMASK);
+               for (i = 0; i < mc->soc->num_intmasks; i++) {
+                       if (mc->soc->num_channels)
+                               mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,
+                                            mc->soc->intmasks[i].reg);
+                       else
+                               mc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);
+               }
        }
 
        if (mc->soc->reset_ops) {

diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c
index 3a061a2d881eae437909a0b72bbfbdcac6a18591..02dd4e26288a1d6ed45c94d5ae805508f800ecbc 100644 (file)
--- a/drivers/memory/tegra/tegra114.c
+++ b/drivers/memory/tegra/tegra114.c
@@ -1101,6 +1101,14 @@ static const struct tegra_mc_reset tegra114_mc_resets[] = {
        TEGRA114_MC_RESET(VI,       0x200, 0x204, 17),
 };
 
+static const struct tegra_mc_intmask tegra114_mc_intmasks[] = {
+       {
+               .reg = MC_INTMASK,
+               .mask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
+                       MC_INT_DECERR_EMEM,
+       },
+};
+
 const struct tegra_mc_soc tegra114_mc_soc = {
        .clients = tegra114_mc_clients,
        .num_clients = ARRAY_SIZE(tegra114_mc_clients),
@@ -1108,8 +1116,8 @@ const struct tegra_mc_soc tegra114_mc_soc = {
        .atom_size = 32,
        .client_id_mask = 0x7f,
        .smmu = &tegra114_smmu_soc,
-       .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
-                  MC_INT_DECERR_EMEM,
+       .intmasks = tegra114_mc_intmasks,
+       .num_intmasks = ARRAY_SIZE(tegra114_mc_intmasks),
        .reset_ops = &tegra_mc_reset_ops_common,
        .resets = tegra114_mc_resets,
        .num_resets = ARRAY_SIZE(tegra114_mc_resets),

diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c
index 4d394889c1e92c89a170f999459e55321f549c9d..df87c503862525b8aeafdec880f815c52deff28b 100644 (file)
--- a/drivers/memory/tegra/tegra124.c
+++ b/drivers/memory/tegra/tegra124.c
@@ -1258,6 +1258,15 @@ static const struct tegra_smmu_soc tegra124_smmu_soc = {
        .num_asids = 128,
 };
 
+static const struct tegra_mc_intmask tegra124_mc_intmasks[] = {
+       {
+               .reg = MC_INTMASK,
+               .mask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
+                       MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
+                       MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
+       },
+};
+
 const struct tegra_mc_soc tegra124_mc_soc = {
        .clients = tegra124_mc_clients,
        .num_clients = ARRAY_SIZE(tegra124_mc_clients),
@@ -1267,9 +1276,8 @@ const struct tegra_mc_soc tegra124_mc_soc = {
        .smmu = &tegra124_smmu_soc,
        .emem_regs = tegra124_mc_emem_regs,
        .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
-       .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
-                  MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
-                  MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
+       .intmasks = tegra124_mc_intmasks,
+       .num_intmasks = ARRAY_SIZE(tegra124_mc_intmasks),
        .reset_ops = &tegra_mc_reset_ops_common,
        .resets = tegra124_mc_resets,
        .num_resets = ARRAY_SIZE(tegra124_mc_resets),
@@ -1297,6 +1305,15 @@ static const struct tegra_smmu_soc tegra132_smmu_soc = {
        .num_asids = 128,
 };
 
+static const struct tegra_mc_intmask tegra132_mc_intmasks[] = {
+       {
+               .reg = MC_INTMASK,
+               .mask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
+                       MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
+                       MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
+       },
+};
+
 const struct tegra_mc_soc tegra132_mc_soc = {
        .clients = tegra124_mc_clients,
        .num_clients = ARRAY_SIZE(tegra124_mc_clients),
@@ -1304,9 +1321,8 @@ const struct tegra_mc_soc tegra132_mc_soc = {
        .atom_size = 32,
        .client_id_mask = 0x7f,
        .smmu = &tegra132_smmu_soc,
-       .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
-                  MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
-                  MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
+       .intmasks = tegra132_mc_intmasks,
+       .num_intmasks = ARRAY_SIZE(tegra132_mc_intmasks),
        .reset_ops = &tegra_mc_reset_ops_common,
        .resets = tegra124_mc_resets,
        .num_resets = ARRAY_SIZE(tegra124_mc_resets),

diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
index 94cad76c52ac84f32bf09aa8101121a9d04bdad9..91d56165605f66511a8a0b5c755bd0c56330c42d 100644 (file)
--- a/drivers/memory/tegra/tegra186.c
+++ b/drivers/memory/tegra/tegra186.c
@@ -901,15 +901,23 @@ static const struct tegra_mc_client tegra186_mc_clients[] = {
        },
 };
 
+static const struct tegra_mc_intmask tegra186_mc_intmasks[] = {
+       {
+               .reg = MC_INTMASK,
+               .mask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
+                       MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
+                       MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
+       },
+};
+
 const struct tegra_mc_soc tegra186_mc_soc = {
        .num_clients = ARRAY_SIZE(tegra186_mc_clients),
        .clients = tegra186_mc_clients,
        .num_address_bits = 40,
        .num_channels = 4,
        .client_id_mask = 0xff,
-       .intmask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
-                  MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
-                  MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
+       .intmasks = tegra186_mc_intmasks,
+       .num_intmasks = ARRAY_SIZE(tegra186_mc_intmasks),
        .ops = &tegra186_mc_ops,
        .ch_intmask = 0x0000000f,
        .global_intstatus_channel_shift = 0,

diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra194.c
index 38852b2a0f4480c10ca1404c5fde0390e54c9ddd..a8cc57690696defb40d4d5f5ff1a0dd73077ddb6 100644 (file)
--- a/drivers/memory/tegra/tegra194.c
+++ b/drivers/memory/tegra/tegra194.c
@@ -1343,16 +1343,23 @@ static const struct tegra_mc_client tegra194_mc_clients[] = {
        },
 };
 
+static const struct tegra_mc_intmask tegra194_mc_intmasks[] = {
+       {
+               .reg = MC_INTMASK,
+               .mask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOUT |
+                       MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
+                       MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
+       },
+};
+
 const struct tegra_mc_soc tegra194_mc_soc = {
        .num_clients = ARRAY_SIZE(tegra194_mc_clients),
        .clients = tegra194_mc_clients,
        .num_address_bits = 40,
        .num_channels = 16,
        .client_id_mask = 0xff,
-       .intmask = MC_INT_DECERR_ROUTE_SANITY |
-                  MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
-                  MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
-                  MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
+       .intmasks = tegra194_mc_intmasks,
+       .num_intmasks = ARRAY_SIZE(tegra194_mc_intmasks),
        .has_addr_hi_reg = true,
        .ops = &tegra186_mc_ops,
        .icc_ops = &tegra_mc_icc_ops,

diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c
index a5cc770437ae24d720d656301cc45ebd4b921e26..ff9e151b5a4c7bce0c8755fe12c53f7851b24561 100644 (file)
--- a/drivers/memory/tegra/tegra20.c
+++ b/drivers/memory/tegra/tegra20.c
@@ -695,7 +695,7 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, void *data)
        unsigned int bit;
 
        /* mask all interrupts to avoid flooding */
-       status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
+       status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmasks[0].mask;
        if (!status)
                return IRQ_NONE;
 
@@ -769,13 +769,21 @@ static const struct tegra_mc_ops tegra20_mc_ops = {
        .probe = tegra20_mc_probe,
 };
 
+static const struct tegra_mc_intmask tegra20_mc_intmasks[] = {
+       {
+               .reg = MC_INTMASK,
+               .mask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE |
+                       MC_INT_DECERR_EMEM,
+       },
+};
+
 const struct tegra_mc_soc tegra20_mc_soc = {
        .clients = tegra20_mc_clients,
        .num_clients = ARRAY_SIZE(tegra20_mc_clients),
        .num_address_bits = 32,
        .client_id_mask = 0x3f,
-       .intmask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE |
-                  MC_INT_DECERR_EMEM,
+       .intmasks = tegra20_mc_intmasks,
+       .num_intmasks = ARRAY_SIZE(tegra20_mc_intmasks),
        .reset_ops = &tegra20_mc_reset_ops,
        .resets = tegra20_mc_resets,
        .num_resets = ARRAY_SIZE(tegra20_mc_resets),

diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index aa606df8a67980076fbf6f134de029eec64b9d1a..f58f3ef6f68191ede7098bfa4dad546ce4de275d 100644 (file)
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -1273,6 +1273,15 @@ static const struct tegra_mc_reset tegra210_mc_resets[] = {
        TEGRA210_MC_RESET(TSECB,     0x970, 0x974, 13),
 };
 
+static const struct tegra_mc_intmask tegra210_mc_intmasks[] = {
+       {
+               .reg = MC_INTMASK,
+               .mask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
+                       MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
+                       MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
+       },
+};
+
 const struct tegra_mc_soc tegra210_mc_soc = {
        .clients = tegra210_mc_clients,
        .num_clients = ARRAY_SIZE(tegra210_mc_clients),
@@ -1280,9 +1289,8 @@ const struct tegra_mc_soc tegra210_mc_soc = {
        .atom_size = 64,
        .client_id_mask = 0xff,
        .smmu = &tegra210_smmu_soc,
-       .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
-                  MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
-                  MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
+       .intmasks = tegra210_mc_intmasks,
+       .num_intmasks = ARRAY_SIZE(tegra210_mc_intmasks),
        .reset_ops = &tegra_mc_reset_ops_common,
        .resets = tegra210_mc_resets,
        .num_resets = ARRAY_SIZE(tegra210_mc_resets),

diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c
index 67d5d4e01a65bd447e40ac3332a4bc23379d27bb..87b22038a5fbff46908c4cbe9052cb8e8975c6b8 100644 (file)
--- a/drivers/memory/tegra/tegra234.c
+++ b/drivers/memory/tegra/tegra234.c
@@ -1132,16 +1132,23 @@ static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = {
        .set = tegra234_mc_icc_set,
 };
 
+static const struct tegra_mc_intmask tegra234_mc_intmasks[] = {
+       {
+               .reg = MC_INTMASK,
+               .mask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOUT |
+                       MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
+                       MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
+       },
+};
+
 const struct tegra_mc_soc tegra234_mc_soc = {
        .num_clients = ARRAY_SIZE(tegra234_mc_clients),
        .clients = tegra234_mc_clients,
        .num_address_bits = 40,
        .num_channels = 16,
        .client_id_mask = 0x1ff,
-       .intmask = MC_INT_DECERR_ROUTE_SANITY |
-                  MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
-                  MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
-                  MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
+       .intmasks = tegra234_mc_intmasks,
+       .num_intmasks = ARRAY_SIZE(tegra234_mc_intmasks),
        .has_addr_hi_reg = true,
        .ops = &tegra186_mc_ops,
        .icc_ops = &tegra234_mc_icc_ops,

diff --git a/drivers/memory/tegra/tegra264.c b/drivers/memory/tegra/tegra264.c
index 5203e6c113727e9cafd58e35f55809b4f6a9951b..172a48b56484a23db0bcb5009974ab4cda7a7bd6 100644 (file)
--- a/drivers/memory/tegra/tegra264.c
+++ b/drivers/memory/tegra/tegra264.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2025, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2025-2026, NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <dt-bindings/memory/nvidia,tegra264.h>
@@ -290,16 +290,23 @@ static const struct tegra_mc_icc_ops tegra264_mc_icc_ops = {
        .set = tegra264_mc_icc_set,
 };
 
+static const struct tegra_mc_intmask tegra264_mc_intmasks[] = {
+       {
+               .reg = MC_INTMASK,
+               .mask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOUT |
+                       MC_INT_DECERR_MTS  | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
+                       MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
+       },
+};
+
 const struct tegra_mc_soc tegra264_mc_soc = {
        .num_clients = ARRAY_SIZE(tegra264_mc_clients),
        .clients = tegra264_mc_clients,
        .num_address_bits = 40,
        .num_channels = 16,
        .client_id_mask = 0x1ff,
-       .intmask = MC_INT_DECERR_ROUTE_SANITY |
-                  MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
-                  MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
-                  MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
+       .intmasks = tegra264_mc_intmasks,
+       .num_intmasks = ARRAY_SIZE(tegra264_mc_intmasks),
        .has_addr_hi_reg = true,
        .ops = &tegra186_mc_ops,
        .icc_ops = &tegra264_mc_icc_ops,

diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c
index 8a26a2f204e9b925e3ae866fac80a938c27ef87e..8389e3af0121302047dcea56659e6219b7d82947 100644 (file)
--- a/drivers/memory/tegra/tegra30.c
+++ b/drivers/memory/tegra/tegra30.c
@@ -1384,6 +1384,14 @@ static const struct tegra_mc_icc_ops tegra30_mc_icc_ops = {
        .set = tegra30_mc_icc_set,
 };
 
+static const struct tegra_mc_intmask tegra30_mc_intmasks[] = {
+       {
+               .reg = MC_INTMASK,
+               .mask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
+                       MC_INT_DECERR_EMEM,
+       },
+};
+
 const struct tegra_mc_soc tegra30_mc_soc = {
        .clients = tegra30_mc_clients,
        .num_clients = ARRAY_SIZE(tegra30_mc_clients),
@@ -1393,8 +1401,8 @@ const struct tegra_mc_soc tegra30_mc_soc = {
        .smmu = &tegra30_smmu_soc,
        .emem_regs = tegra30_mc_emem_regs,
        .num_emem_regs = ARRAY_SIZE(tegra30_mc_emem_regs),
-       .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
-                  MC_INT_DECERR_EMEM,
+       .intmasks = tegra30_mc_intmasks,
+       .num_intmasks = ARRAY_SIZE(tegra30_mc_intmasks),
        .reset_ops = &tegra_mc_reset_ops_common,
        .resets = tegra30_mc_resets,
        .num_resets = ARRAY_SIZE(tegra30_mc_resets),

diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
index b9b1763b10b5fce2da5e7fa0d8baa5b0b32cf07e..e6da035d1306d81fcde8e044ce24bb7627bb31db 100644 (file)
--- a/include/soc/tegra/mc.h
+++ b/include/soc/tegra/mc.h
@@ -185,6 +185,11 @@ struct tegra_mc_regs {
        unsigned int err_route_add;
 };
 
+struct tegra_mc_intmask {
+       u32 reg;
+       u32 mask;
+};
+
 struct tegra_mc_soc {
        const struct tegra_mc_client *clients;
        unsigned int num_clients;
@@ -202,7 +207,6 @@ struct tegra_mc_soc {
 
        const struct tegra_smmu_soc *smmu;
 
-       u32 intmask;
        u32 ch_intmask;
        u32 global_intstatus_channel_shift;
        bool has_addr_hi_reg;
@@ -219,6 +223,8 @@ struct tegra_mc_soc {
        unsigned int num_interrupts;
        unsigned int mc_addr_hi_mask;
        unsigned int mc_err_status_type_mask;
+       const struct tegra_mc_intmask *intmasks;
+       unsigned int num_intmasks;
 };
 
 struct tegra_mc {