net: xilinx_axi: Add axi ethernet support on Zynq and ZynqMP

This patch adds support of axi ethernet for Zynq and ZynqMP
platforms. The endianess conversion is not needed here and
hence io operations are performed using writel and readl
directly for Zynq and ZynqMP.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index fb3c56cd670eed995dfc69d9db111edf868f53bf..0c478db9bb907109c1c0f322ebd0ce7f66afb26e 100644 (file)
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -72,6 +72,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define DMAALIGN       128
 
+#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_ZYNQ)
+#undef out_be32
+#undef in_be32
+#define out_be32(off, val)     writel(val, off)
+#define in_be32(off)           readl(off)
+#endif
+
 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
 
 /* Reflect dma offsets */