]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible values
authorGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 24 Oct 2022 10:03:52 +0000 (12:03 +0200)
committerSasha Levin <sashal@kernel.org>
Tue, 26 Mar 2024 22:21:20 +0000 (18:21 -0400)
[ Upstream commit a1721bbbdb5c6687d157f8b8714bba837f6028ac ]

Despite the name, R-Car V3U is the first member of the R-Car Gen4
family.  Hence update the compatible properties in various device nodes
to include family-specific compatible values for R-Car Gen4 instead of
R-Car Gen3:
  - DMAC,
  - (H)SCIF,
  - I2C,
  - IPMMU,
  - WDT.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/73cea9d5e1a6639422c67e4df4285042e31c9fd5.1651497071.git.geert+renesas@glider.be
Stable-dep-of: 0c51912331f8 ("arm64: dts: renesas: r8a779a0: Correct avb[01] reg sizes")
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/arm64/boot/dts/renesas/r8a779a0.dtsi

index 26899fb768a739883d56ed74977db055e623a6b5..c7d1b79692c115e7bc5888347c9c34cdf13e51e1 100644 (file)
 
                avb0: ethernet@e6800000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6800000 0 0x800>;
                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 
                avb1: ethernet@e6810000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6810000 0 0x800>;
                        interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
 
                avb2: ethernet@e6820000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6820000 0 0x1000>;
                        interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
 
                avb3: ethernet@e6830000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6830000 0 0x1000>;
                        interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
 
                avb4: ethernet@e6840000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6840000 0 0x1000>;
                        interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
 
                avb5: ethernet@e6850000 {
                        compatible = "renesas,etheravb-r8a779a0",
-                                    "renesas,etheravb-rcar-gen3";
+                                    "renesas,etheravb-rcar-gen4";
                        reg = <0 0xe6850000 0 0x1000>;
                        interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
 
                msiof0: spi@e6e90000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6e90000 0 0x0064>;
                        interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 618>;
 
                msiof1: spi@e6ea0000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6ea0000 0 0x0064>;
                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 619>;
 
                msiof2: spi@e6c00000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6c00000 0 0x0064>;
                        interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 620>;
 
                msiof3: spi@e6c10000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6c10000 0 0x0064>;
                        interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 621>;
 
                msiof4: spi@e6c20000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6c20000 0 0x0064>;
                        interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 622>;
 
                msiof5: spi@e6c28000 {
                        compatible = "renesas,msiof-r8a779a0",
-                                    "renesas,rcar-gen3-msiof";
+                                    "renesas,rcar-gen4-msiof";
                        reg = <0 0xe6c28000 0 0x0064>;
                        interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 623>;