drm/i915/dp: Verify branch devices' overall pixel throughput/line width

Read out the branch devices' maximum overall DSC pixel throughput and
line width and verify the mode's corresponding pixel clock and hactive
period against these.

v2: Use drm helpers to query the throughput/line-width caps. (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reported-and-tested-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/20250930182450.563016-6-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 029c47743f8b18189b61669170e5b66afcd045ad..99d2c312369287096cb0ca12db1cb2af1d57d9cd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -552,6 +552,14 @@ struct intel_connector {
 
                u8 dsc_hblank_expansion_quirk:1;
                u8 dsc_decompression_enabled:1;
+
+               struct {
+                       struct {
+                               int rgb_yuv444;
+                               int yuv422_420;
+                       } overall_throughput;
+                       int max_line_width;
+               } dsc_branch_caps;
        } dp;
 
        struct {

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2dcc20bcfa0ba6969bc975cbebedf4fcc9a1c182..9de9356302f9770f8fbc9b894b58082f7d5a28ce 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1016,6 +1016,20 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
        int tp_rgb_yuv444;
        int tp_yuv422_420;
 
+       /*
+        * TODO: Use the throughput value specific to the actual RGB/YUV
+        * format of the output.
+        * The RGB/YUV444 throughput value should be always either equal
+        * or smaller than the YUV422/420 value, but let's not depend on
+        * this assumption.
+        */
+       if (mode_clock > max(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444,
+                            connector->dp.dsc_branch_caps.overall_throughput.yuv422_420))
+               return 0;
+
+       if (mode_hdisplay > connector->dp.dsc_branch_caps.max_line_width)
+               return 0;
+
        /*
         * TODO: Pass the total pixel rate of all the streams transferred to
         * an MST tiled display, calculate the total slice count for all tiles
@@ -4180,6 +4194,33 @@ static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
                    dsc_dpcd);
 }
 
+static void init_dsc_overall_throughput_limits(struct intel_connector *connector, bool is_branch)
+{
+       u8 branch_caps[DP_DSC_BRANCH_CAP_SIZE];
+       int line_width;
+
+       connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 = INT_MAX;
+       connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 = INT_MAX;
+       connector->dp.dsc_branch_caps.max_line_width = INT_MAX;
+
+       if (!is_branch)
+               return;
+
+       if (drm_dp_dpcd_read_data(connector->dp.dsc_decompression_aux,
+                                 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, branch_caps,
+                                 sizeof(branch_caps)) != 0)
+               return;
+
+       connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 =
+               drm_dp_dsc_branch_max_overall_throughput(branch_caps, true) ? : INT_MAX;
+
+       connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 =
+               drm_dp_dsc_branch_max_overall_throughput(branch_caps, false) ? : INT_MAX;
+
+       line_width = drm_dp_dsc_branch_max_line_width(branch_caps);
+       connector->dp.dsc_branch_caps.max_line_width = line_width > 0 ? line_width : INT_MAX;
+}
+
 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
                               const struct drm_dp_desc *desc, bool is_branch,
                               struct intel_connector *connector)
@@ -4195,6 +4236,8 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
        /* Clear fec_capable to avoid using stale values */
        connector->dp.fec_capability = 0;
 
+       memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps));
+
        if (dpcd_rev < DP_DPCD_REV_14)
                return;
 
@@ -4209,6 +4252,11 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
 
        drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",
                    connector->dp.fec_capability);
+
+       if (!(connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED))
+               return;
+
+       init_dsc_overall_throughput_limits(connector, is_branch);
 }
 
 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
@@ -4217,6 +4265,9 @@ static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *
                return;
 
        intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
+
+       if (connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)
+               init_dsc_overall_throughput_limits(connector, false);
 }
 
 static void