Xilinx: ARM: SD: speed up SD by removing the clock divide

It's not clear why it was was running so slow, but maybe
it was needed for EP107. Speed it up now.

diff --git a/board/xilinx/dfe/mmc.c b/board/xilinx/dfe/mmc.c
index 91b21db01129013c88cbe1bb3a979beb3482d58d..dd952fc58409f4cee85e2a15888d4bb5c347ffd5 100755 (executable)
--- a/board/xilinx/dfe/mmc.c
+++ b/board/xilinx/dfe/mmc.c
@@ -73,7 +73,7 @@ static void init_port(void)
        sd_out8(SD_PWR_CTRL_R, SD_POWER_33|SD_POWER_ON);
 
        /* Enable Internal clock and wait for it to stablilize */
-       clk = (0x40 << SD_DIV_SHIFT) | SD_CLK_INT_EN;
+       clk = SD_CLK_INT_EN;
        sd_out16(SD_CLK_CTL_R, clk);
        do {
                clk = sd_in16(SD_CLK_CTL_R);