drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/CONTEXT_TOGGLE flag macro

Move the PHY_C20_CONTEXT_TOGGLE flag's definition under the register containing
the flag and refer to the flag always by its name instead of a plain bit number.

v2: Amend commit log to match what the patch does. (Jani)

Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20251015125446.3931198-4-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 9492661f1645ccd7634f969c7c53898414e444d1..a7aee098e7b9a7ee81fd9f5c64e4edc3e5d22c25 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2628,7 +2628,8 @@ static void intel_c20_pll_program(struct intel_display *display,
        int i;
 
        /* 1. Read current context selection */
-       cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0);
+       cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) &
+               PHY_C20_CONTEXT_TOGGLE;
 
        /*
         * 2. If there is a protocol switch from HDMI to DP or vice versa, clear
@@ -2719,7 +2720,8 @@ static void intel_c20_pll_program(struct intel_display *display,
         * the updated programming toggle context bit
         */
        intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
-                     BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED);
+                     PHY_C20_CONTEXT_TOGGLE, cntx ? 0 : PHY_C20_CONTEXT_TOGGLE,
+                     MB_WRITE_COMMITTED);
 }
 
 static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index ad2f7fb3beaec13775971d24a55179df98a3336d..5bd1e02b531391de4cb93e52c47348d373e155bd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -301,8 +301,8 @@
 #define   PHY_C20_IS_DP                        REG_BIT8(6)
 #define   PHY_C20_DP_RATE_MASK         REG_GENMASK8(4, 1)
 #define   PHY_C20_DP_RATE(val)         REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
-#define PHY_C20_VDR_HDMI_RATE          0xD01
 #define   PHY_C20_CONTEXT_TOGGLE       REG_BIT8(0)
+#define PHY_C20_VDR_HDMI_RATE          0xD01
 #define PHY_C20_VDR_CUSTOM_WIDTH       0xD02
 #define   PHY_C20_CUSTOM_WIDTH_MASK    REG_GENMASK(1, 0)
 #define   PHY_C20_CUSTOM_WIDTH(val)    REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)