--- /dev/null
+From 6687c201fdc3139315c2ea7ef96c157672805cdc Mon Sep 17 00:00:00 2001
+From: Nick Hudson <skrll@netbsd.org>
+Date: Thu, 12 Mar 2020 09:03:45 +0000
+Subject: ARM: bcm2835-rpi-zero-w: Add missing pinctrl name
+
+From: Nick Hudson <skrll@netbsd.org>
+
+commit 6687c201fdc3139315c2ea7ef96c157672805cdc upstream.
+
+Define the sdhci pinctrl state as "default" so it gets applied
+correctly and to match all other RPis.
+
+Fixes: 2c7c040c73e9 ("ARM: dts: bcm2835: Add Raspberry Pi Zero W")
+Signed-off-by: Nick Hudson <skrll@netbsd.org>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
++++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
+@@ -112,6 +112,7 @@
+ &sdhci {
+ #address-cells = <1>;
+ #size-cells = <0>;
++ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
--- /dev/null
+From 55c7c0621078bd73e9d4d2a11eb36e61bc6fe998 Mon Sep 17 00:00:00 2001
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Date: Thu, 19 Mar 2020 20:00:13 +0100
+Subject: ARM: dts: bcm283x: Fix vc4's firmware bus DMA limitations
+
+From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+
+commit 55c7c0621078bd73e9d4d2a11eb36e61bc6fe998 upstream.
+
+The bus is virtual and devices have to inherit their DMA constraints
+from the underlying interconnect. So add an empty dma-ranges property to
+the bus node, implying the firmware bus' DMA constraints are identical to
+its parent's.
+
+Fixes: 7dbe8c62ceeb ("ARM: dts: Add minimal Raspberry Pi 4 support")
+Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/bcm2835-rpi.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
++++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
+@@ -15,6 +15,7 @@
+ firmware: firmware {
+ compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
+ mboxes = <&mailbox>;
++ dma-ranges;
+ };
+
+ power: power {
--- /dev/null
+From 636b45b8efa91db05553840b6c0120d6fa6b94fa Mon Sep 17 00:00:00 2001
+From: Marco Felsch <m.felsch@pengutronix.de>
+Date: Thu, 27 Feb 2020 12:02:46 +0100
+Subject: ARM: dts: imx6: phycore-som: fix arm and soc minimum voltage
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Marco Felsch <m.felsch@pengutronix.de>
+
+commit 636b45b8efa91db05553840b6c0120d6fa6b94fa upstream.
+
+The current set minimum voltage of 730000µV seems to be wrong. I don't
+know the document which specifies that but the imx6qdl datasheets says
+that the minimum voltage should be 0.925V for VDD_ARM (LDO bypassed,
+lowest opp) and 1.15V for VDD_SOC (LDO bypassed, lowest opp).
+
+Fixes: ddec5d1c0047 ("ARM: dts: imx6: Add initial support for phyCORE-i.MX 6 SOM")
+Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
+@@ -107,14 +107,14 @@
+ regulators {
+ vdd_arm: buck1 {
+ regulator-name = "vdd_arm";
+- regulator-min-microvolt = <730000>;
++ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1380000>;
+ regulator-always-on;
+ };
+
+ vdd_soc: buck2 {
+ regulator-name = "vdd_soc";
+- regulator-min-microvolt = <730000>;
++ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1380000>;
+ regulator-always-on;
+ };
--- /dev/null
+From 0c5220a3c1242c7a2451570ed5f5af69620aac75 Mon Sep 17 00:00:00 2001
+From: Arthur Demchenkov <spinal.by@gmail.com>
+Date: Sun, 8 Mar 2020 22:19:33 +0300
+Subject: ARM: dts: N900: fix onenand timings
+
+From: Arthur Demchenkov <spinal.by@gmail.com>
+
+commit 0c5220a3c1242c7a2451570ed5f5af69620aac75 upstream.
+
+Commit a758f50f10cf ("mtd: onenand: omap2: Configure driver from DT")
+started using DT specified timings for GPMC, and as a result the
+OneNAND stopped working on N900 as we had wrong values in the DT.
+Fix by updating the values to bootloader timings that have been tested
+to be working on Nokia N900 with OneNAND manufacturers: Samsung,
+Numonyx.
+
+Fixes: a758f50f10cf ("mtd: onenand: omap2: Configure driver from DT")
+Signed-off-by: Arthur Demchenkov <spinal.by@gmail.com>
+Tested-by: Merlijn Wajer <merlijn@wizzup.org>
+Reviewed-by: Roger Quadros <rogerq@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/omap3-n900.dts | 44 ++++++++++++++++++++++++---------------
+ 1 file changed, 28 insertions(+), 16 deletions(-)
+
+--- a/arch/arm/boot/dts/omap3-n900.dts
++++ b/arch/arm/boot/dts/omap3-n900.dts
+@@ -849,34 +849,46 @@
+ compatible = "ti,omap2-onenand";
+ reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
+
++ /*
++ * These timings are based on CONFIG_OMAP_GPMC_DEBUG=y reported
++ * bootloader set values when booted with v5.1
++ * (OneNAND Manufacturer: Samsung):
++ *
++ * cs0 GPMC_CS_CONFIG1: 0xfb001202
++ * cs0 GPMC_CS_CONFIG2: 0x00111100
++ * cs0 GPMC_CS_CONFIG3: 0x00020200
++ * cs0 GPMC_CS_CONFIG4: 0x11001102
++ * cs0 GPMC_CS_CONFIG5: 0x03101616
++ * cs0 GPMC_CS_CONFIG6: 0x90060000
++ */
+ gpmc,sync-read;
+ gpmc,sync-write;
+ gpmc,burst-length = <16>;
+ gpmc,burst-read;
+ gpmc,burst-wrap;
+ gpmc,burst-write;
+- gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
+- gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
++ gpmc,device-width = <2>;
++ gpmc,mux-add-data = <2>;
+ gpmc,cs-on-ns = <0>;
+- gpmc,cs-rd-off-ns = <87>;
+- gpmc,cs-wr-off-ns = <87>;
++ gpmc,cs-rd-off-ns = <102>;
++ gpmc,cs-wr-off-ns = <102>;
+ gpmc,adv-on-ns = <0>;
+- gpmc,adv-rd-off-ns = <10>;
+- gpmc,adv-wr-off-ns = <10>;
+- gpmc,oe-on-ns = <15>;
+- gpmc,oe-off-ns = <87>;
++ gpmc,adv-rd-off-ns = <12>;
++ gpmc,adv-wr-off-ns = <12>;
++ gpmc,oe-on-ns = <12>;
++ gpmc,oe-off-ns = <102>;
+ gpmc,we-on-ns = <0>;
+- gpmc,we-off-ns = <87>;
+- gpmc,rd-cycle-ns = <112>;
+- gpmc,wr-cycle-ns = <112>;
+- gpmc,access-ns = <81>;
+- gpmc,page-burst-access-ns = <15>;
++ gpmc,we-off-ns = <102>;
++ gpmc,rd-cycle-ns = <132>;
++ gpmc,wr-cycle-ns = <132>;
++ gpmc,access-ns = <96>;
++ gpmc,page-burst-access-ns = <18>;
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <0>;
+ gpmc,wait-monitoring-ns = <0>;
+- gpmc,clk-activation-ns = <5>;
+- gpmc,wr-data-mux-bus-ns = <30>;
+- gpmc,wr-access-ns = <81>;
++ gpmc,clk-activation-ns = <6>;
++ gpmc,wr-data-mux-bus-ns = <36>;
++ gpmc,wr-access-ns = <96>;
+ gpmc,sync-clk-ps = <15000>;
+
+ /*
--- /dev/null
+From deeabb4c1341a12bf8b599e6a2f4cfa4fd74738c Mon Sep 17 00:00:00 2001
+From: Sungbo Eo <mans0n@gorani.run>
+Date: Sat, 21 Mar 2020 23:36:53 +0900
+Subject: ARM: dts: oxnas: Fix clear-mask property
+
+From: Sungbo Eo <mans0n@gorani.run>
+
+commit deeabb4c1341a12bf8b599e6a2f4cfa4fd74738c upstream.
+
+Disable all rps-irq interrupts during driver initialization to prevent
+an accidental interrupt on GIC.
+
+Fixes: 84316f4ef141 ("ARM: boot: dts: Add Oxford Semiconductor OX810SE dtsi")
+Fixes: 38d4a53733f5 ("ARM: dts: Add support for OX820 and Pogoplug V3")
+Signed-off-by: Sungbo Eo <mans0n@gorani.run>
+Acked-by: Neil Armstrong <narmstrong@baylibre.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/ox810se.dtsi | 4 ++--
+ arch/arm/boot/dts/ox820.dtsi | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/arm/boot/dts/ox810se.dtsi
++++ b/arch/arm/boot/dts/ox810se.dtsi
+@@ -323,8 +323,8 @@
+ interrupt-controller;
+ reg = <0 0x200>;
+ #interrupt-cells = <1>;
+- valid-mask = <0xFFFFFFFF>;
+- clear-mask = <0>;
++ valid-mask = <0xffffffff>;
++ clear-mask = <0xffffffff>;
+ };
+
+ timer0: timer@200 {
+--- a/arch/arm/boot/dts/ox820.dtsi
++++ b/arch/arm/boot/dts/ox820.dtsi
+@@ -240,8 +240,8 @@
+ reg = <0 0x200>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+- valid-mask = <0xFFFFFFFF>;
+- clear-mask = <0>;
++ valid-mask = <0xffffffff>;
++ clear-mask = <0xffffffff>;
+ };
+
+ timer0: timer@200 {
--- /dev/null
+From fe3a04824f75786e39ed74e82fb6cb2534c95fe4 Mon Sep 17 00:00:00 2001
+From: Chen-Yu Tsai <wens@csie.org>
+Date: Wed, 11 Mar 2020 01:47:07 +0800
+Subject: ARM: dts: sun8i: r40: Move AHCI device node based on address order
+
+From: Chen-Yu Tsai <wens@csie.org>
+
+commit fe3a04824f75786e39ed74e82fb6cb2534c95fe4 upstream.
+
+When the AHCI device node was added, it was added in the wrong location
+in the device tree file. The device nodes should be sorted by register
+address.
+
+Move the device node to before EHCI1, where it belongs.
+
+Fixes: 41c64d3318aa ("ARM: dts: sun8i: r40: add sata node")
+Acked-by: Maxime Ripard <mripard@kernel.org>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+Signed-off-by: Chen-Yu Tsai <wens@csie.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/boot/dts/sun8i-r40.dtsi | 21 ++++++++++-----------
+ 1 file changed, 10 insertions(+), 11 deletions(-)
+
+--- a/arch/arm/boot/dts/sun8i-r40.dtsi
++++ b/arch/arm/boot/dts/sun8i-r40.dtsi
+@@ -275,6 +275,16 @@
+ resets = <&ccu RST_BUS_CE>;
+ };
+
++ ahci: sata@1c18000 {
++ compatible = "allwinner,sun8i-r40-ahci";
++ reg = <0x01c18000 0x1000>;
++ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
++ resets = <&ccu RST_BUS_SATA>;
++ reset-names = "ahci";
++ status = "disabled";
++ };
++
+ ehci1: usb@1c19000 {
+ compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
+ reg = <0x01c19000 0x100>;
+@@ -566,17 +576,6 @@
+ #size-cells = <0>;
+ };
+
+- ahci: sata@1c18000 {
+- compatible = "allwinner,sun8i-r40-ahci";
+- reg = <0x01c18000 0x1000>;
+- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
+- resets = <&ccu RST_BUS_SATA>;
+- reset-names = "ahci";
+- status = "disabled";
+-
+- };
+-
+ gmac: ethernet@1c50000 {
+ compatible = "allwinner,sun8i-r40-gmac";
+ syscon = <&ccu>;
--- /dev/null
+From 6f5459da2b8736720afdbd67c4bd2d1edba7d0e3 Mon Sep 17 00:00:00 2001
+From: Ilie Halip <ilie.halip@gmail.com>
+Date: Thu, 19 Mar 2020 23:45:28 +0200
+Subject: arm64: alternative: fix build with clang integrated assembler
+
+From: Ilie Halip <ilie.halip@gmail.com>
+
+commit 6f5459da2b8736720afdbd67c4bd2d1edba7d0e3 upstream.
+
+Building an arm64 defconfig with clang's integrated assembler, this error
+occurs:
+ <instantiation>:2:2: error: unrecognized instruction mnemonic
+ _ASM_EXTABLE 9999b, 9f
+ ^
+ arch/arm64/mm/cache.S:50:1: note: while in macro instantiation
+ user_alt 9f, "dc cvau, x4", "dc civac, x4", 0
+ ^
+
+While GNU as seems fine with case-sensitive macro instantiations, clang
+doesn't, so use the actual macro name (_asm_extable) as in the rest of
+the file.
+
+Also checked that the generated assembly matches the GCC output.
+
+Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
+Tested-by: Nick Desaulniers <ndesaulniers@google.com>
+Fixes: 290622efc76e ("arm64: fix "dc cvau" cache operation on errata-affected core")
+Link: https://github.com/ClangBuiltLinux/linux/issues/924
+Signed-off-by: Ilie Halip <ilie.halip@gmail.com>
+Signed-off-by: Will Deacon <will@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm64/include/asm/alternative.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/include/asm/alternative.h
++++ b/arch/arm64/include/asm/alternative.h
+@@ -221,7 +221,7 @@ alternative_endif
+
+ .macro user_alt, label, oldinstr, newinstr, cond
+ 9999: alternative_insn "\oldinstr", "\newinstr", \cond
+- _ASM_EXTABLE 9999b, \label
++ _asm_extable 9999b, \label
+ .endm
+
+ /*
--- /dev/null
+From 4022d808c45277693ea86478fab1f081ebf997e8 Mon Sep 17 00:00:00 2001
+From: Madalin Bucur <madalin.bucur@oss.nxp.com>
+Date: Mon, 16 Mar 2020 14:05:57 +0200
+Subject: arm64: dts: ls1043a-rdb: correct RGMII delay mode to rgmii-id
+
+From: Madalin Bucur <madalin.bucur@oss.nxp.com>
+
+commit 4022d808c45277693ea86478fab1f081ebf997e8 upstream.
+
+The correct setting for the RGMII ports on LS1043ARDB is to
+enable delay on both Rx and Tx so the interface mode used must
+be PHY_INTERFACE_MODE_RGMII_ID.
+
+Since commit 1b3047b5208a80 ("net: phy: realtek: add support for
+configuring the RX delay on RTL8211F") the Realtek 8211F PHY driver
+has control over the RGMII RX delay and it is disabling it for
+RGMII_TXID. The LS1043ARDB uses two such PHYs in RGMII_ID mode but
+in the device tree the mode was described as "rgmii_txid".
+This issue was not apparent at the time as the PHY driver took the
+same action for RGMII_TXID and RGMII_ID back then but it became
+visible (RX no longer working) after the above patch.
+
+Changing the phy-connection-type to "rgmii-id" to address the issue.
+
+Fixes: bf02f2ffe59c ("arm64: dts: add LS1043A DPAA FMan support")
+Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+@@ -119,12 +119,12 @@
+
+ ethernet@e4000 {
+ phy-handle = <&rgmii_phy1>;
+- phy-connection-type = "rgmii-txid";
++ phy-connection-type = "rgmii-id";
+ };
+
+ ethernet@e6000 {
+ phy-handle = <&rgmii_phy2>;
+- phy-connection-type = "rgmii-txid";
++ phy-connection-type = "rgmii-id";
+ };
+
+ ethernet@e8000 {
--- /dev/null
+From d79e9d7c1e4ba5f95f2ff3541880c40ea9722212 Mon Sep 17 00:00:00 2001
+From: Madalin Bucur <madalin.bucur@oss.nxp.com>
+Date: Mon, 16 Mar 2020 14:05:58 +0200
+Subject: arm64: dts: ls1046ardb: set RGMII interfaces to RGMII_ID mode
+
+From: Madalin Bucur <madalin.bucur@oss.nxp.com>
+
+commit d79e9d7c1e4ba5f95f2ff3541880c40ea9722212 upstream.
+
+The correct setting for the RGMII ports on LS1046ARDB is to
+enable delay on both Rx and Tx so the interface mode used must
+be PHY_INTERFACE_MODE_RGMII_ID.
+
+Since commit 1b3047b5208a80 ("net: phy: realtek: add support for
+configuring the RX delay on RTL8211F") the Realtek 8211F PHY driver
+has control over the RGMII RX delay and it is disabling it for
+RGMII_TXID. The LS1046ARDB uses two such PHYs in RGMII_ID mode but
+in the device tree the mode was described as "rgmii".
+
+Changing the phy-connection-type to "rgmii-id" to address the issue.
+
+Fixes: 3fa395d2c48a ("arm64: dts: add LS1046A DPAA FMan nodes")
+Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+@@ -131,12 +131,12 @@
+ &fman0 {
+ ethernet@e4000 {
+ phy-handle = <&rgmii_phy1>;
+- phy-connection-type = "rgmii";
++ phy-connection-type = "rgmii-id";
+ };
+
+ ethernet@e6000 {
+ phy-handle = <&rgmii_phy2>;
+- phy-connection-type = "rgmii";
++ phy-connection-type = "rgmii-id";
+ };
+
+ ethernet@e8000 {
--- /dev/null
+From a0ae04a25650fd51b7106e742d27333e502173c6 Mon Sep 17 00:00:00 2001
+From: Leonard Crestez <leonard.crestez@nxp.com>
+Date: Thu, 20 Feb 2020 18:29:32 +0200
+Subject: clk: imx: Align imx sc clock msg structs to 4
+
+From: Leonard Crestez <leonard.crestez@nxp.com>
+
+commit a0ae04a25650fd51b7106e742d27333e502173c6 upstream.
+
+The imx SC api strongly assumes that messages are composed out of
+4-bytes words but some of our message structs have odd sizeofs.
+
+This produces many oopses with CONFIG_KASAN=y.
+
+Fix by marking with __aligned(4).
+
+Fixes: fe37b4820417 ("clk: imx: add scu clock common part")
+Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
+Link: https://lkml.kernel.org/r/10e97a04980d933b2cfecb6b124bf9046b6e4f16.1582216144.git.leonard.crestez@nxp.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/imx/clk-scu.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/imx/clk-scu.c
++++ b/drivers/clk/imx/clk-scu.c
+@@ -43,12 +43,12 @@ struct imx_sc_msg_req_set_clock_rate {
+ __le32 rate;
+ __le16 resource;
+ u8 clk;
+-} __packed;
++} __packed __aligned(4);
+
+ struct req_get_clock_rate {
+ __le16 resource;
+ u8 clk;
+-} __packed;
++} __packed __aligned(4);
+
+ struct resp_get_clock_rate {
+ __le32 rate;
+@@ -121,7 +121,7 @@ struct imx_sc_msg_req_clock_enable {
+ u8 clk;
+ u8 enable;
+ u8 autog;
+-} __packed;
++} __packed __aligned(4);
+
+ static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
+ {
--- /dev/null
+From 8400ab8896324641243b57fc49b448023c07409a Mon Sep 17 00:00:00 2001
+From: Leonard Crestez <leonard.crestez@nxp.com>
+Date: Thu, 20 Feb 2020 18:29:33 +0200
+Subject: clk: imx: Align imx sc clock parent msg structs to 4
+
+From: Leonard Crestez <leonard.crestez@nxp.com>
+
+commit 8400ab8896324641243b57fc49b448023c07409a upstream.
+
+The imx SC api strongly assumes that messages are composed out of
+4-bytes words but some of our message structs have odd sizeofs.
+
+This produces many oopses with CONFIG_KASAN=y.
+
+Fix by marking with __aligned(4).
+
+Fixes: 666aed2d13ee ("clk: imx: scu: add set parent support")
+Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
+Link: https://lkml.kernel.org/r/aad021e432b3062c142973d09b766656eec18fde.1582216144.git.leonard.crestez@nxp.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/imx/clk-scu.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/imx/clk-scu.c
++++ b/drivers/clk/imx/clk-scu.c
+@@ -84,7 +84,7 @@ struct imx_sc_msg_get_clock_parent {
+ struct req_get_clock_parent {
+ __le16 resource;
+ u8 clk;
+- } __packed req;
++ } __packed __aligned(4) req;
+ struct resp_get_clock_parent {
+ u8 parent;
+ } resp;
--- /dev/null
+From 5f3d9b07b9bb4679922f0b2e2baa770e74a6bbd3 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Fri, 21 Feb 2020 09:10:30 -0800
+Subject: clk: ti: am43xx: Fix clock parent for RTC clock
+
+From: Tony Lindgren <tony@atomide.com>
+
+commit 5f3d9b07b9bb4679922f0b2e2baa770e74a6bbd3 upstream.
+
+Currently enabling clkctrl clock on am4 can fail for RTC as the clock
+parent is wrong for RTC.
+
+Fixes: 76a1049b84dd ("clk: ti: am43xx: add new clkctrl data for am43xx")
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Link: https://lkml.kernel.org/r/20200221171030.39326-1-tony@atomide.com
+Acked-by: Tero Kristo <t-kristo@ti.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/ti/clk-43xx.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/ti/clk-43xx.c
++++ b/drivers/clk/ti/clk-43xx.c
+@@ -78,7 +78,7 @@ static const struct omap_clkctrl_reg_dat
+ };
+
+ static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
+- { AM4_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
++ { AM4_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ick" },
+ { 0 },
+ };
+
--- /dev/null
+From 0c625ccfe6f754d0896b8881f5c85bcb81699f1f Mon Sep 17 00:00:00 2001
+From: Hans de Goede <hdegoede@redhat.com>
+Date: Mon, 2 Mar 2020 12:12:25 +0100
+Subject: gpiolib: acpi: Add quirk to ignore EC wakeups on HP x2 10 CHT + AXP288 model
+
+From: Hans de Goede <hdegoede@redhat.com>
+
+commit 0c625ccfe6f754d0896b8881f5c85bcb81699f1f upstream.
+
+There are at least 3 models of the HP x2 10 models:
+
+Bay Trail SoC + AXP288 PMIC
+Cherry Trail SoC + AXP288 PMIC
+Cherry Trail SoC + TI PMIC
+
+Like on the other HP x2 10 models we need to ignore wakeup for ACPI GPIO
+events on the external embedded-controller pin to avoid spurious wakeups
+on the HP x2 10 CHT + AXP288 model too.
+
+This commit adds an extra DMI based quirk for the HP x2 10 CHT + AXP288
+model, ignoring wakeups for ACPI GPIO events on the EC interrupt pin
+on this model. This fixes spurious wakeups from suspend on this model.
+
+Fixes: aa23ca3d98f7 ("gpiolib: acpi: Add honor_wakeup module-option + quirk mechanism")
+Reported-and-tested-by: Marc Lehmann <schmorp@schmorp.de>
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+Link: https://lore.kernel.org/r/20200302111225.6641-4-hdegoede@redhat.com
+Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpio/gpiolib-acpi.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/drivers/gpio/gpiolib-acpi.c
++++ b/drivers/gpio/gpiolib-acpi.c
+@@ -1437,6 +1437,21 @@ static const struct dmi_system_id gpioli
+ .ignore_wake = "INT33FC:02@28",
+ },
+ },
++ {
++ /*
++ * HP X2 10 models with Cherry Trail SoC + AXP288 PMIC use an
++ * external embedded-controller connected via I2C + an ACPI GPIO
++ * event handler on INT33FF:01 pin 0, causing spurious wakeups.
++ */
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "HP"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion x2 Detachable"),
++ DMI_MATCH(DMI_BOARD_NAME, "813E"),
++ },
++ .driver_data = &(struct acpi_gpiolib_dmi_quirk) {
++ .ignore_wake = "INT33FF:01@0",
++ },
++ },
+ {} /* Terminating entry */
+ };
+
--- /dev/null
+From 0433ae556ec8fb588a0735ddb09d3eb9806df479 Mon Sep 17 00:00:00 2001
+From: Golan Ben Ami <golan.ben.ami@intel.com>
+Date: Wed, 18 Mar 2020 08:12:54 +0200
+Subject: iwlwifi: don't send GEO_TX_POWER_LIMIT if no wgds table
+
+From: Golan Ben Ami <golan.ben.ami@intel.com>
+
+commit 0433ae556ec8fb588a0735ddb09d3eb9806df479 upstream.
+
+The GEO_TX_POWER_LIMIT command was sent although
+there is no wgds table, so the fw got wrong SAR values
+from the driver.
+
+Fix this by avoiding sending the command if no wgds
+tables are available.
+
+Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com>
+Fixes: 39c1a9728f93 ("iwlwifi: refactor the SAR tables from mvm to acpi")
+Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
+Tested-By: Jonathan McDowell <noodles@earth.li>
+Tested-by: Len Brown <len.brown@intel.com>
+Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
+Link: https://lore.kernel.org/r/iwlwifi.20200318081237.46db40617cc6.Id5cf852ec8c5dbf20ba86bad7b165a0c828f8b2e@changeid
+Cc: Felipe Contreras <felipe.contreras@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/net/wireless/intel/iwlwifi/fw/acpi.c | 14 ++++++++------
+ drivers/net/wireless/intel/iwlwifi/fw/acpi.h | 14 ++++++++------
+ drivers/net/wireless/intel/iwlwifi/mvm/fw.c | 9 ++++++++-
+ 3 files changed, 24 insertions(+), 13 deletions(-)
+
+--- a/drivers/net/wireless/intel/iwlwifi/fw/acpi.c
++++ b/drivers/net/wireless/intel/iwlwifi/fw/acpi.c
+@@ -6,7 +6,7 @@
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2017 Intel Deutschland GmbH
+- * Copyright (C) 2019 Intel Corporation
++ * Copyright (C) 2019 - 2020 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+@@ -27,7 +27,7 @@
+ * BSD LICENSE
+ *
+ * Copyright(c) 2017 Intel Deutschland GmbH
+- * Copyright (C) 2019 Intel Corporation
++ * Copyright (C) 2019 - 2020 Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+@@ -491,13 +491,13 @@ int iwl_validate_sar_geo_profile(struct
+ }
+ IWL_EXPORT_SYMBOL(iwl_validate_sar_geo_profile);
+
+-void iwl_sar_geo_init(struct iwl_fw_runtime *fwrt,
+- struct iwl_per_chain_offset_group *table)
++int iwl_sar_geo_init(struct iwl_fw_runtime *fwrt,
++ struct iwl_per_chain_offset_group *table)
+ {
+ int ret, i, j;
+
+ if (!iwl_sar_geo_support(fwrt))
+- return;
++ return -EOPNOTSUPP;
+
+ ret = iwl_sar_get_wgds_table(fwrt);
+ if (ret < 0) {
+@@ -505,7 +505,7 @@ void iwl_sar_geo_init(struct iwl_fw_runt
+ "Geo SAR BIOS table invalid or unavailable. (%d)\n",
+ ret);
+ /* we don't fail if the table is not available */
+- return;
++ return -ENOENT;
+ }
+
+ BUILD_BUG_ON(ACPI_NUM_GEO_PROFILES * ACPI_WGDS_NUM_BANDS *
+@@ -530,5 +530,7 @@ void iwl_sar_geo_init(struct iwl_fw_runt
+ i, j, value[1], value[2], value[0]);
+ }
+ }
++
++ return 0;
+ }
+ IWL_EXPORT_SYMBOL(iwl_sar_geo_init);
+--- a/drivers/net/wireless/intel/iwlwifi/fw/acpi.h
++++ b/drivers/net/wireless/intel/iwlwifi/fw/acpi.h
+@@ -6,7 +6,7 @@
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2017 Intel Deutschland GmbH
+- * Copyright(c) 2018 - 2019 Intel Corporation
++ * Copyright(c) 2018 - 2020 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+@@ -27,7 +27,7 @@
+ * BSD LICENSE
+ *
+ * Copyright(c) 2017 Intel Deutschland GmbH
+- * Copyright(c) 2018 - 2019 Intel Corporation
++ * Copyright(c) 2018 - 2020 Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+@@ -171,8 +171,9 @@ bool iwl_sar_geo_support(struct iwl_fw_r
+ int iwl_validate_sar_geo_profile(struct iwl_fw_runtime *fwrt,
+ struct iwl_host_cmd *cmd);
+
+-void iwl_sar_geo_init(struct iwl_fw_runtime *fwrt,
+- struct iwl_per_chain_offset_group *table);
++int iwl_sar_geo_init(struct iwl_fw_runtime *fwrt,
++ struct iwl_per_chain_offset_group *table);
++
+ #else /* CONFIG_ACPI */
+
+ static inline void *iwl_acpi_get_object(struct device *dev, acpi_string method)
+@@ -243,9 +244,10 @@ static inline int iwl_validate_sar_geo_p
+ return -ENOENT;
+ }
+
+-static inline void iwl_sar_geo_init(struct iwl_fw_runtime *fwrt,
+- struct iwl_per_chain_offset_group *table)
++static inline int iwl_sar_geo_init(struct iwl_fw_runtime *fwrt,
++ struct iwl_per_chain_offset_group *table)
+ {
++ return -ENOENT;
+ }
+
+ #endif /* CONFIG_ACPI */
+--- a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c
++++ b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c
+@@ -749,10 +749,17 @@ static int iwl_mvm_sar_geo_init(struct i
+ u16 cmd_wide_id = WIDE_ID(PHY_OPS_GROUP, GEO_TX_POWER_LIMIT);
+ union geo_tx_power_profiles_cmd cmd;
+ u16 len;
++ int ret;
+
+ cmd.geo_cmd.ops = cpu_to_le32(IWL_PER_CHAIN_OFFSET_SET_TABLES);
+
+- iwl_sar_geo_init(&mvm->fwrt, cmd.geo_cmd.table);
++ ret = iwl_sar_geo_init(&mvm->fwrt, cmd.geo_cmd.table);
++ /*
++ * It is a valid scenario to not support SAR, or miss wgds table,
++ * but in that case there is no need to send the command.
++ */
++ if (ret)
++ return 0;
+
+ cmd.geo_cmd.table_revision = cpu_to_le32(mvm->fwrt.geo_rev);
+
--- /dev/null
+From e886274031200bb60965c1b9c49b7acda56a93bd Mon Sep 17 00:00:00 2001
+From: Ilya Dryomov <idryomov@gmail.com>
+Date: Tue, 10 Mar 2020 16:19:01 +0100
+Subject: libceph: fix alloc_msg_with_page_vector() memory leaks
+
+From: Ilya Dryomov <idryomov@gmail.com>
+
+commit e886274031200bb60965c1b9c49b7acda56a93bd upstream.
+
+Make it so that CEPH_MSG_DATA_PAGES data item can own pages,
+fixing a bunch of memory leaks for a page vector allocated in
+alloc_msg_with_page_vector(). Currently, only watch-notify
+messages trigger this allocation, and normally the page vector
+is freed either in handle_watch_notify() or by the caller of
+ceph_osdc_notify(). But if the message is freed before that
+(e.g. if the session faults while reading in the message or
+if the notify is stale), we leak the page vector.
+
+This was supposed to be fixed by switching to a message-owned
+pagelist, but that never happened.
+
+Fixes: 1907920324f1 ("libceph: support for sending notifies")
+Reported-by: Roman Penyaev <rpenyaev@suse.de>
+Signed-off-by: Ilya Dryomov <idryomov@gmail.com>
+Reviewed-by: Roman Penyaev <rpenyaev@suse.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ include/linux/ceph/messenger.h | 7 ++++---
+ net/ceph/messenger.c | 9 +++++++--
+ net/ceph/osd_client.c | 14 +++-----------
+ 3 files changed, 14 insertions(+), 16 deletions(-)
+
+--- a/include/linux/ceph/messenger.h
++++ b/include/linux/ceph/messenger.h
+@@ -175,9 +175,10 @@ struct ceph_msg_data {
+ #endif /* CONFIG_BLOCK */
+ struct ceph_bvec_iter bvec_pos;
+ struct {
+- struct page **pages; /* NOT OWNER. */
++ struct page **pages;
+ size_t length; /* total # bytes */
+ unsigned int alignment; /* first page */
++ bool own_pages;
+ };
+ struct ceph_pagelist *pagelist;
+ };
+@@ -356,8 +357,8 @@ extern void ceph_con_keepalive(struct ce
+ extern bool ceph_con_keepalive_expired(struct ceph_connection *con,
+ unsigned long interval);
+
+-extern void ceph_msg_data_add_pages(struct ceph_msg *msg, struct page **pages,
+- size_t length, size_t alignment);
++void ceph_msg_data_add_pages(struct ceph_msg *msg, struct page **pages,
++ size_t length, size_t alignment, bool own_pages);
+ extern void ceph_msg_data_add_pagelist(struct ceph_msg *msg,
+ struct ceph_pagelist *pagelist);
+ #ifdef CONFIG_BLOCK
+--- a/net/ceph/messenger.c
++++ b/net/ceph/messenger.c
+@@ -3248,12 +3248,16 @@ static struct ceph_msg_data *ceph_msg_da
+
+ static void ceph_msg_data_destroy(struct ceph_msg_data *data)
+ {
+- if (data->type == CEPH_MSG_DATA_PAGELIST)
++ if (data->type == CEPH_MSG_DATA_PAGES && data->own_pages) {
++ int num_pages = calc_pages_for(data->alignment, data->length);
++ ceph_release_page_vector(data->pages, num_pages);
++ } else if (data->type == CEPH_MSG_DATA_PAGELIST) {
+ ceph_pagelist_release(data->pagelist);
++ }
+ }
+
+ void ceph_msg_data_add_pages(struct ceph_msg *msg, struct page **pages,
+- size_t length, size_t alignment)
++ size_t length, size_t alignment, bool own_pages)
+ {
+ struct ceph_msg_data *data;
+
+@@ -3265,6 +3269,7 @@ void ceph_msg_data_add_pages(struct ceph
+ data->pages = pages;
+ data->length = length;
+ data->alignment = alignment & ~PAGE_MASK;
++ data->own_pages = own_pages;
+
+ msg->data_length += length;
+ }
+--- a/net/ceph/osd_client.c
++++ b/net/ceph/osd_client.c
+@@ -962,7 +962,7 @@ static void ceph_osdc_msg_data_add(struc
+ BUG_ON(length > (u64) SIZE_MAX);
+ if (length)
+ ceph_msg_data_add_pages(msg, osd_data->pages,
+- length, osd_data->alignment);
++ length, osd_data->alignment, false);
+ } else if (osd_data->type == CEPH_OSD_DATA_TYPE_PAGELIST) {
+ BUG_ON(!length);
+ ceph_msg_data_add_pagelist(msg, osd_data->pagelist);
+@@ -4436,9 +4436,7 @@ static void handle_watch_notify(struct c
+ CEPH_MSG_DATA_PAGES);
+ *lreq->preply_pages = data->pages;
+ *lreq->preply_len = data->length;
+- } else {
+- ceph_release_page_vector(data->pages,
+- calc_pages_for(0, data->length));
++ data->own_pages = false;
+ }
+ }
+ lreq->notify_finish_error = return_code;
+@@ -5500,9 +5498,6 @@ out_unlock_osdc:
+ return m;
+ }
+
+-/*
+- * TODO: switch to a msg-owned pagelist
+- */
+ static struct ceph_msg *alloc_msg_with_page_vector(struct ceph_msg_header *hdr)
+ {
+ struct ceph_msg *m;
+@@ -5516,7 +5511,6 @@ static struct ceph_msg *alloc_msg_with_p
+
+ if (data_len) {
+ struct page **pages;
+- struct ceph_osd_data osd_data;
+
+ pages = ceph_alloc_page_vector(calc_pages_for(0, data_len),
+ GFP_NOIO);
+@@ -5525,9 +5519,7 @@ static struct ceph_msg *alloc_msg_with_p
+ return NULL;
+ }
+
+- ceph_osd_data_pages_init(&osd_data, pages, data_len, 0, false,
+- false);
+- ceph_osdc_msg_data_add(m, &osd_data);
++ ceph_msg_data_add_pages(m, pages, data_len, 0, true);
+ }
+
+ return m;
--- /dev/null
+From 8262e6f9b1034ede34548a04dec4c302d92c9497 Mon Sep 17 00:00:00 2001
+From: Marek Vasut <marex@denx.de>
+Date: Wed, 25 Mar 2020 15:25:47 +0100
+Subject: net: ks8851-ml: Fix IO operations, again
+
+From: Marek Vasut <marex@denx.de>
+
+commit 8262e6f9b1034ede34548a04dec4c302d92c9497 upstream.
+
+This patch reverts 58292104832f ("net: ks8851-ml: Fix 16-bit IO operation")
+and edacb098ea9c ("net: ks8851-ml: Fix 16-bit data access"), because it
+turns out these were only necessary due to buggy hardware. This patch adds
+a check for such a buggy hardware to prevent any such mistakes again.
+
+While working further on the KS8851 driver, it came to light that the
+KS8851-16MLL is capable of switching bus endianness by a hardware strap,
+EESK pin. If this strap is incorrect, the IO accesses require such endian
+swapping as is being reverted by this patch. Such swapping also impacts
+the performance significantly.
+
+Hence, in addition to removing it, detect that the hardware is broken,
+report to user, and fail to bind with such hardware.
+
+Fixes: 58292104832f ("net: ks8851-ml: Fix 16-bit IO operation")
+Fixes: edacb098ea9c ("net: ks8851-ml: Fix 16-bit data access")
+Signed-off-by: Marek Vasut <marex@denx.de>
+Cc: David S. Miller <davem@davemloft.net>
+Cc: Lukas Wunner <lukas@wunner.de>
+Cc: Petr Stetiar <ynezz@true.cz>
+Cc: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/net/ethernet/micrel/ks8851_mll.c | 56 ++++++++++++++++++++++++++++---
+ 1 file changed, 52 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/ethernet/micrel/ks8851_mll.c
++++ b/drivers/net/ethernet/micrel/ks8851_mll.c
+@@ -157,6 +157,50 @@ static int msg_enable;
+ */
+
+ /**
++ * ks_check_endian - Check whether endianness of the bus is correct
++ * @ks : The chip information
++ *
++ * The KS8851-16MLL EESK pin allows selecting the endianness of the 16bit
++ * bus. To maintain optimum performance, the bus endianness should be set
++ * such that it matches the endianness of the CPU.
++ */
++
++static int ks_check_endian(struct ks_net *ks)
++{
++ u16 cider;
++
++ /*
++ * Read CIDER register first, however read it the "wrong" way around.
++ * If the endian strap on the KS8851-16MLL in incorrect and the chip
++ * is operating in different endianness than the CPU, then the meaning
++ * of BE[3:0] byte-enable bits is also swapped such that:
++ * BE[3,2,1,0] becomes BE[1,0,3,2]
++ *
++ * Luckily for us, the byte-enable bits are the top four MSbits of
++ * the address register and the CIDER register is at offset 0xc0.
++ * Hence, by reading address 0xc0c0, which is not impacted by endian
++ * swapping, we assert either BE[3:2] or BE[1:0] while reading the
++ * CIDER register.
++ *
++ * If the bus configuration is correct, reading 0xc0c0 asserts
++ * BE[3:2] and this read returns 0x0000, because to read register
++ * with bottom two LSbits of address set to 0, BE[1:0] must be
++ * asserted.
++ *
++ * If the bus configuration is NOT correct, reading 0xc0c0 asserts
++ * BE[1:0] and this read returns non-zero 0x8872 value.
++ */
++ iowrite16(BE3 | BE2 | KS_CIDER, ks->hw_addr_cmd);
++ cider = ioread16(ks->hw_addr);
++ if (!cider)
++ return 0;
++
++ netdev_err(ks->netdev, "incorrect EESK endian strap setting\n");
++
++ return -EINVAL;
++}
++
++/**
+ * ks_rdreg16 - read 16 bit register from device
+ * @ks : The chip information
+ * @offset: The register address
+@@ -166,7 +210,7 @@ static int msg_enable;
+
+ static u16 ks_rdreg16(struct ks_net *ks, int offset)
+ {
+- ks->cmd_reg_cache = (u16)offset | ((BE3 | BE2) >> (offset & 0x02));
++ ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02));
+ iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
+ return ioread16(ks->hw_addr);
+ }
+@@ -181,7 +225,7 @@ static u16 ks_rdreg16(struct ks_net *ks,
+
+ static void ks_wrreg16(struct ks_net *ks, int offset, u16 value)
+ {
+- ks->cmd_reg_cache = (u16)offset | ((BE3 | BE2) >> (offset & 0x02));
++ ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02));
+ iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
+ iowrite16(value, ks->hw_addr);
+ }
+@@ -197,7 +241,7 @@ static inline void ks_inblk(struct ks_ne
+ {
+ len >>= 1;
+ while (len--)
+- *wptr++ = be16_to_cpu(ioread16(ks->hw_addr));
++ *wptr++ = (u16)ioread16(ks->hw_addr);
+ }
+
+ /**
+@@ -211,7 +255,7 @@ static inline void ks_outblk(struct ks_n
+ {
+ len >>= 1;
+ while (len--)
+- iowrite16(cpu_to_be16(*wptr++), ks->hw_addr);
++ iowrite16(*wptr++, ks->hw_addr);
+ }
+
+ static void ks_disable_int(struct ks_net *ks)
+@@ -1218,6 +1262,10 @@ static int ks8851_probe(struct platform_
+ goto err_free;
+ }
+
++ err = ks_check_endian(ks);
++ if (err)
++ goto err_free;
++
+ netdev->irq = platform_get_irq(pdev, 0);
+
+ if ((int)netdev->irq < 0) {
--- /dev/null
+From db2c549407d4a76563c579e4768f7d6d32afefba Mon Sep 17 00:00:00 2001
+From: disconnect3d <dominik.b.czarnota@gmail.com>
+Date: Mon, 9 Mar 2020 11:48:53 +0100
+Subject: perf map: Fix off by one in strncpy() size argument
+
+From: disconnect3d <dominik.b.czarnota@gmail.com>
+
+commit db2c549407d4a76563c579e4768f7d6d32afefba upstream.
+
+This patch fixes an off-by-one error in strncpy size argument in
+tools/perf/util/map.c. The issue is that in:
+
+ strncmp(filename, "/system/lib/", 11)
+
+the passed string literal: "/system/lib/" has 12 bytes (without the NULL
+byte) and the passed size argument is 11. As a result, the logic won't
+match the ending "/" byte and will pass filepaths that are stored in
+other directories e.g. "/system/libmalicious/bin" or just
+"/system/libmalicious".
+
+This functionality seems to be present only on Android. I assume the
+/system/ directory is only writable by the root user, so I don't think
+this bug has much (or any) security impact.
+
+Fixes: eca818369996 ("perf tools: Add automatic remapping of Android libraries")
+Signed-off-by: disconnect3d <dominik.b.czarnota@gmail.com>
+Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
+Cc: Changbin Du <changbin.du@intel.com>
+Cc: Jiri Olsa <jolsa@redhat.com>
+Cc: John Keeping <john@metanate.com>
+Cc: Mark Rutland <mark.rutland@arm.com>
+Cc: Michael Lentine <mlentine@google.com>
+Cc: Namhyung Kim <namhyung@kernel.org>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Song Liu <songliubraving@fb.com>
+Cc: Stephane Eranian <eranian@google.com>
+Link: http://lore.kernel.org/lkml/20200309104855.3775-1-dominik.b.czarnota@gmail.com
+Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ tools/perf/util/map.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/tools/perf/util/map.c
++++ b/tools/perf/util/map.c
+@@ -89,7 +89,7 @@ static inline bool replace_android_lib(c
+ return true;
+ }
+
+- if (!strncmp(filename, "/system/lib/", 11)) {
++ if (!strncmp(filename, "/system/lib/", 12)) {
+ char *ndk, *app;
+ const char *arch;
+ size_t ndk_length;
platform-x86-pmc_atom-add-lex-2i385sw-to-critclk_systems-dmi-table.patch
bpf-explicitly-memset-the-bpf_attr-structure.patch
bpf-explicitly-memset-some-bpf-info-structures-declared-on-the-stack.patch
+iwlwifi-don-t-send-geo_tx_power_limit-if-no-wgds-table.patch
+gpiolib-acpi-add-quirk-to-ignore-ec-wakeups-on-hp-x2-10-cht-axp288-model.patch
+net-ks8851-ml-fix-io-operations-again.patch
+clk-imx-align-imx-sc-clock-msg-structs-to-4.patch
+clk-imx-align-imx-sc-clock-parent-msg-structs-to-4.patch
+clk-ti-am43xx-fix-clock-parent-for-rtc-clock.patch
+libceph-fix-alloc_msg_with_page_vector-memory-leaks.patch
+arm64-alternative-fix-build-with-clang-integrated-assembler.patch
+perf-map-fix-off-by-one-in-strncpy-size-argument.patch
+arm-dts-oxnas-fix-clear-mask-property.patch
+arm-dts-bcm283x-fix-vc4-s-firmware-bus-dma-limitations.patch
+arm-bcm2835-rpi-zero-w-add-missing-pinctrl-name.patch
+arm-dts-imx6-phycore-som-fix-arm-and-soc-minimum-voltage.patch
+arm-dts-n900-fix-onenand-timings.patch
+arm-dts-sun8i-r40-move-ahci-device-node-based-on-address-order.patch
+arm64-dts-ls1043a-rdb-correct-rgmii-delay-mode-to-rgmii-id.patch
+arm64-dts-ls1046ardb-set-rgmii-interfaces-to-rgmii_id-mode.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
