clk: mediatek: mt7988: convert to struct mtk_parent

Convert all parent clock arrays to use struct mtk_parent. This will
allow us to simplify core code later by having only one possible data
type for mux parent arrays.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260317-clk-mtk-unify-mux-parents-v3-6-a4760f5b0a80@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>

diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 83f7c559e317c336cc5b797ddb9f309bcdb0b7fb..21d194ed8076d0043fda71074d3ebdca16b4799d 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -444,51 +444,75 @@ static const struct mtk_composite topckgen_mtk_muxes[] = {
 };
 
 /* INFRASYS MUX PARENTS */
-static const int infra_mux_uart0_parents[] = { CLK_TOP_INFRA_F26M_SEL,
-                                              CLK_TOP_UART_SEL };
+static const struct mtk_parent infra_mux_uart0_parents[] = {
+       TOP_PARENT(CLK_TOP_INFRA_F26M_SEL),
+       TOP_PARENT(CLK_TOP_UART_SEL),
+};
 
-static const int infra_mux_uart1_parents[] = { CLK_TOP_INFRA_F26M_SEL,
-                                              CLK_TOP_UART_SEL };
+static const struct mtk_parent infra_mux_uart1_parents[] = {
+       TOP_PARENT(CLK_TOP_INFRA_F26M_SEL),
+       TOP_PARENT(CLK_TOP_UART_SEL),
+};
 
-static const int infra_mux_uart2_parents[] = { CLK_TOP_INFRA_F26M_SEL,
-                                              CLK_TOP_UART_SEL };
+static const struct mtk_parent infra_mux_uart2_parents[] = {
+       TOP_PARENT(CLK_TOP_INFRA_F26M_SEL),
+       TOP_PARENT(CLK_TOP_UART_SEL),
+};
 
-static const int infra_mux_spi0_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPI_SEL };
+static const struct mtk_parent infra_mux_spi0_parents[] = {
+       TOP_PARENT(CLK_TOP_I2C_SEL),
+       TOP_PARENT(CLK_TOP_SPI_SEL),
+};
 
-static const int infra_mux_spi1_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPIM_MST_SEL };
+static const struct mtk_parent infra_mux_spi1_parents[] = {
+       TOP_PARENT(CLK_TOP_I2C_SEL),
+       TOP_PARENT(CLK_TOP_SPIM_MST_SEL),
+};
 
-static const int infra_pwm_bck_parents[] = { CLK_TOP_RTC_32P7K,
-                                            CLK_TOP_INFRA_F26M_SEL, CLK_TOP_SYSAXI_SEL,
-                                            CLK_TOP_PWM_SEL };
+static const struct mtk_parent infra_pwm_bck_parents[] = {
+       TOP_PARENT(CLK_TOP_RTC_32P7K),
+       TOP_PARENT(CLK_TOP_INFRA_F26M_SEL),
+       TOP_PARENT(CLK_TOP_SYSAXI_SEL),
+       TOP_PARENT(CLK_TOP_PWM_SEL),
+};
 
-static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
-       CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
-       CLK_TOP_PEXTP_TL_SEL
+static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
+       TOP_PARENT(CLK_TOP_RTC_32P7K),
+       TOP_PARENT(CLK_TOP_INFRA_F26M_SEL),
+       TOP_PARENT(CLK_TOP_INFRA_F26M_SEL),
+       TOP_PARENT(CLK_TOP_PEXTP_TL_SEL),
 };
 
-static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
-       CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
-       CLK_TOP_PEXTP_TL_P1_SEL
+static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
+       TOP_PARENT(CLK_TOP_RTC_32P7K),
+       TOP_PARENT(CLK_TOP_INFRA_F26M_SEL),
+       TOP_PARENT(CLK_TOP_INFRA_F26M_SEL),
+       TOP_PARENT(CLK_TOP_PEXTP_TL_P1_SEL),
 };
 
-static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = {
-       CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
-       CLK_TOP_PEXTP_TL_P2_SEL
+static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p2_parents[] = {
+       TOP_PARENT(CLK_TOP_RTC_32P7K),
+       TOP_PARENT(CLK_TOP_INFRA_F26M_SEL),
+       TOP_PARENT(CLK_TOP_INFRA_F26M_SEL),
+       TOP_PARENT(CLK_TOP_PEXTP_TL_P2_SEL),
 };
 
-static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
-       CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
-       CLK_TOP_PEXTP_TL_P3_SEL
+static const struct mtk_parent infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
+       TOP_PARENT(CLK_TOP_RTC_32P7K),
+       TOP_PARENT(CLK_TOP_INFRA_F26M_SEL),
+       TOP_PARENT(CLK_TOP_INFRA_F26M_SEL),
+       TOP_PARENT(CLK_TOP_PEXTP_TL_P3_SEL),
 };
 
 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width)                  \
        {                                                                      \
                .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0,   \
                .mux_clr_reg = _reg + 0x4, .mux_shift = _shift,                \
-               .mux_mask = BIT(_width) - 1, .parent = _parents,               \
+               .mux_mask = BIT(_width) - 1,                                   \
+               .parent_flags = _parents,                                      \
                .gate_shift = -1, .upd_shift = -1,                             \
                .num_parents = ARRAY_SIZE(_parents),                           \
-               .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN,             \
+               .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED,                \
        }
 
 /* INFRA MUX */