--- /dev/null
+From f523f74eac1897b13c05c88ce6e5de0a7c34578b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon, 31 Jan 2011 16:48:52 -0500
+Subject: drm/radeon/kms: add new pll algo for avivo asics
+
+From: Alex Deucher <alexdeucher@gmail.com>
+
+commit f523f74eac1897b13c05c88ce6e5de0a7c34578b upstream.
+
+Based on the vbios code. This should hopefully
+fix the pll problems on a number of avivo asics
+once it's enabled.
+
+Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/atombios_crtc.c | 4
+ drivers/gpu/drm/radeon/radeon_display.c | 123 ++++++++++++++++++++++++++--
+ drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 6 -
+ drivers/gpu/drm/radeon/radeon_mode.h | 23 +++--
+ 4 files changed, 137 insertions(+), 19 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/atombios_crtc.c
++++ b/drivers/gpu/drm/radeon/atombios_crtc.c
+@@ -915,8 +915,8 @@ static void atombios_crtc_set_pll(struct
+ /* adjust pixel clock as needed */
+ adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
+
+- radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
+- &ref_div, &post_div);
++ radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
++ &ref_div, &post_div);
+
+ atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
+
+--- a/drivers/gpu/drm/radeon/radeon_display.c
++++ b/drivers/gpu/drm/radeon/radeon_display.c
+@@ -448,6 +448,115 @@ static int radeon_ddc_dump(struct drm_co
+ return ret;
+ }
+
++/* avivo */
++static void avivo_get_fb_div(struct radeon_pll *pll,
++ u32 target_clock,
++ u32 post_div,
++ u32 ref_div,
++ u32 *fb_div,
++ u32 *frac_fb_div)
++{
++ u32 tmp = post_div * ref_div;
++
++ tmp *= target_clock;
++ *fb_div = tmp / pll->reference_freq;
++ *frac_fb_div = tmp % pll->reference_freq;
++}
++
++static u32 avivo_get_post_div(struct radeon_pll *pll,
++ u32 target_clock)
++{
++ u32 vco, post_div, tmp;
++
++ if (pll->flags & RADEON_PLL_USE_POST_DIV)
++ return pll->post_div;
++
++ if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
++ if (pll->flags & RADEON_PLL_IS_LCD)
++ vco = pll->lcd_pll_out_min;
++ else
++ vco = pll->pll_out_min;
++ } else {
++ if (pll->flags & RADEON_PLL_IS_LCD)
++ vco = pll->lcd_pll_out_max;
++ else
++ vco = pll->pll_out_max;
++ }
++
++ post_div = vco / target_clock;
++ tmp = vco % target_clock;
++
++ if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
++ if (tmp)
++ post_div++;
++ } else {
++ if (!tmp)
++ post_div--;
++ }
++
++ return post_div;
++}
++
++#define MAX_TOLERANCE 10
++
++void radeon_compute_pll_avivo(struct radeon_pll *pll,
++ u32 freq,
++ u32 *dot_clock_p,
++ u32 *fb_div_p,
++ u32 *frac_fb_div_p,
++ u32 *ref_div_p,
++ u32 *post_div_p)
++{
++ u32 target_clock = freq / 10;
++ u32 post_div = avivo_get_post_div(pll, target_clock);
++ u32 ref_div = pll->min_ref_div;
++ u32 fb_div = 0, frac_fb_div = 0, tmp;
++
++ if (pll->flags & RADEON_PLL_USE_REF_DIV)
++ ref_div = pll->reference_div;
++
++ if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
++ avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
++ frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
++ if (frac_fb_div >= 5) {
++ frac_fb_div -= 5;
++ frac_fb_div = frac_fb_div / 10;
++ frac_fb_div++;
++ }
++ if (frac_fb_div >= 10) {
++ fb_div++;
++ frac_fb_div = 0;
++ }
++ } else {
++ while (ref_div <= pll->max_ref_div) {
++ avivo_get_fb_div(pll, target_clock, post_div, ref_div,
++ &fb_div, &frac_fb_div);
++ if (frac_fb_div >= (pll->reference_freq / 2))
++ fb_div++;
++ frac_fb_div = 0;
++ tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
++ tmp = (tmp * 10000) / target_clock;
++
++ if (tmp > (10000 + MAX_TOLERANCE))
++ ref_div++;
++ else if (tmp >= (10000 - MAX_TOLERANCE))
++ break;
++ else
++ ref_div++;
++ }
++ }
++
++ *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
++ (ref_div * post_div * 10);
++ *fb_div_p = fb_div;
++ *frac_fb_div_p = frac_fb_div;
++ *ref_div_p = ref_div;
++ *post_div_p = post_div;
++ DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
++ *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
++}
++
++/* pre-avivo */
+ static inline uint32_t radeon_div(uint64_t n, uint32_t d)
+ {
+ uint64_t mod;
+@@ -458,13 +567,13 @@ static inline uint32_t radeon_div(uint64
+ return n;
+ }
+
+-void radeon_compute_pll(struct radeon_pll *pll,
+- uint64_t freq,
+- uint32_t *dot_clock_p,
+- uint32_t *fb_div_p,
+- uint32_t *frac_fb_div_p,
+- uint32_t *ref_div_p,
+- uint32_t *post_div_p)
++void radeon_compute_pll_legacy(struct radeon_pll *pll,
++ uint64_t freq,
++ uint32_t *dot_clock_p,
++ uint32_t *fb_div_p,
++ uint32_t *frac_fb_div_p,
++ uint32_t *ref_div_p,
++ uint32_t *post_div_p)
+ {
+ uint32_t min_ref_div = pll->min_ref_div;
+ uint32_t max_ref_div = pll->max_ref_div;
+--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
++++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+@@ -778,9 +778,9 @@ static void radeon_set_pll(struct drm_cr
+ DRM_DEBUG_KMS("\n");
+
+ if (!use_bios_divs) {
+- radeon_compute_pll(pll, mode->clock,
+- &freq, &feedback_div, &frac_fb_div,
+- &reference_div, &post_divider);
++ radeon_compute_pll_legacy(pll, mode->clock,
++ &freq, &feedback_div, &frac_fb_div,
++ &reference_div, &post_divider);
+
+ for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
+ if (post_div->divider == post_divider)
+--- a/drivers/gpu/drm/radeon/radeon_mode.h
++++ b/drivers/gpu/drm/radeon/radeon_mode.h
+@@ -149,6 +149,7 @@ struct radeon_tmds_pll {
+ #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
+ #define RADEON_PLL_USE_POST_DIV (1 << 12)
+ #define RADEON_PLL_IS_LCD (1 << 13)
++#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
+
+ struct radeon_pll {
+ /* reference frequency */
+@@ -510,13 +511,21 @@ extern bool radeon_atombios_get_asic_ss_
+ struct radeon_atom_ss *ss,
+ int id, u32 clock);
+
+-extern void radeon_compute_pll(struct radeon_pll *pll,
+- uint64_t freq,
+- uint32_t *dot_clock_p,
+- uint32_t *fb_div_p,
+- uint32_t *frac_fb_div_p,
+- uint32_t *ref_div_p,
+- uint32_t *post_div_p);
++extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
++ uint64_t freq,
++ uint32_t *dot_clock_p,
++ uint32_t *fb_div_p,
++ uint32_t *frac_fb_div_p,
++ uint32_t *ref_div_p,
++ uint32_t *post_div_p);
++
++extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
++ u32 freq,
++ u32 *dot_clock_p,
++ u32 *fb_div_p,
++ u32 *frac_fb_div_p,
++ u32 *ref_div_p,
++ u32 *post_div_p);
+
+ extern void radeon_setup_encoder_clones(struct drm_device *dev);
+
--- /dev/null
+From 51d4bf840a27fe02c883ddc6d9708af056773769 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon, 31 Jan 2011 16:48:51 -0500
+Subject: drm/radeon/kms: add pll debugging output
+
+From: Alex Deucher <alexdeucher@gmail.com>
+
+commit 51d4bf840a27fe02c883ddc6d9708af056773769 upstream.
+
+Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/radeon_display.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/radeon_display.c
++++ b/drivers/gpu/drm/radeon/radeon_display.c
+@@ -633,6 +633,10 @@ void radeon_compute_pll(struct radeon_pl
+ *frac_fb_div_p = best_frac_feedback_div;
+ *ref_div_p = best_ref_div;
+ *post_div_p = best_post_div;
++ DRM_DEBUG_KMS("%d %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
++ freq, best_freq / 1000, best_feedback_div, best_frac_feedback_div,
++ best_ref_div, best_post_div);
++
+ }
+
+ static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
--- /dev/null
+From f598aa7593427ffe3a61e7767c34bd695a5e7ed0 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher@gmail.com>
+Date: Tue, 4 Jan 2011 00:43:39 -0500
+Subject: drm/radeon/kms: add quirk for Mac Radeon HD 2600 card
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alex Deucher <alexdeucher@gmail.com>
+
+commit f598aa7593427ffe3a61e7767c34bd695a5e7ed0 upstream.
+
+Reported-by: 屋国遥 <hyagni@gmail.com>
+Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/radeon_atombios.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/radeon_atombios.c
++++ b/drivers/gpu/drm/radeon/radeon_atombios.c
+@@ -388,6 +388,17 @@ static bool radeon_atom_apply_quirks(str
+ *line_mux = 0x90;
+ }
+
++ /* mac rv630 */
++ if ((dev->pdev->device == 0x9588) &&
++ (dev->pdev->subsystem_vendor == 0x106b) &&
++ (dev->pdev->subsystem_device == 0x00a6)) {
++ if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
++ (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
++ *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
++ *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
++ }
++ }
++
+ /* ASUS HD 3600 XT board lists the DVI port as HDMI */
+ if ((dev->pdev->device == 0x9598) &&
+ (dev->pdev->subsystem_vendor == 0x1043) &&
--- /dev/null
+From 2f299d5de02da3ffb1f9e1a05c91dcd1173ebd3c Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher@gmail.com>
+Date: Tue, 4 Jan 2011 17:42:20 -0500
+Subject: drm/radeon/kms: adjust quirk for acer laptop
+
+From: Alex Deucher <alexdeucher@gmail.com>
+
+commit 2f299d5de02da3ffb1f9e1a05c91dcd1173ebd3c upstream.
+
+Acer laptop (TravelMate 5730G) has an HDMI connector
+on the laptop and a DVI connector on the docking station
+and both share the same encoder, hpd pin, and ddc line.
+The bios connector table reflects this and is technically
+correct, however, we drop the DVI connector here since
+xrandr has no concept of encoders (only crtcs and connectors)
+and will try and drive both connectors with different crtcs
+which isn't possible on the hardware side and leaves no crtcs
+for LVDS or VGA.
+
+Fixes:
+https://bugs.freedesktop.org/show_bug.cgi?id=32732
+
+Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/radeon_atombios.c | 21 +++++++++++----------
+ 1 file changed, 11 insertions(+), 10 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_atombios.c
++++ b/drivers/gpu/drm/radeon/radeon_atombios.c
+@@ -313,7 +313,6 @@ static bool radeon_atom_apply_quirks(str
+ uint16_t *line_mux,
+ struct radeon_hpd *hpd)
+ {
+- struct radeon_device *rdev = dev->dev_private;
+
+ /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
+ if ((dev->pdev->device == 0x791e) &&
+@@ -436,21 +435,23 @@ static bool radeon_atom_apply_quirks(str
+ }
+ }
+
+- /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
++ /* Acer laptop (Acer TravelMate 5730G) has an HDMI port
++ * on the laptop and a DVI port on the docking station and
++ * both share the same encoder, hpd pin, and ddc line.
++ * So while the bios table is technically correct,
++ * we drop the DVI port here since xrandr has no concept of
++ * encoders and will try and drive both connectors
++ * with different crtcs which isn't possible on the hardware
++ * side and leaves no crtcs for LVDS or VGA.
++ */
+ if ((dev->pdev->device == 0x95c4) &&
+ (dev->pdev->subsystem_vendor == 0x1025) &&
+ (dev->pdev->subsystem_device == 0x013c)) {
+- struct radeon_gpio_rec gpio;
+-
+ if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
+ (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
+- gpio = radeon_lookup_gpio(rdev, 6);
+- *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
++ /* actually it's a DVI-D port not DVI-I */
+ *connector_type = DRM_MODE_CONNECTOR_DVID;
+- } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
+- (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
+- gpio = radeon_lookup_gpio(rdev, 7);
+- *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
++ return false;
+ }
+ }
+
--- /dev/null
+From 619efb105924d8cafa0c1dd9389e9ab506f5425d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon, 31 Jan 2011 16:48:53 -0500
+Subject: drm/radeon/kms: Enable new pll calculation for avivo+ asics
+
+From: Alex Deucher <alexdeucher@gmail.com>
+
+commit 619efb105924d8cafa0c1dd9389e9ab506f5425d upstream.
+
+New algo is used for r5xx+ and legacy is used for
+r1xx-r4xx, rv515.
+
+I've tested on all relevant GPUs and monitors that I
+have access to and have found no problems.
+
+Fixes:
+https://bugzilla.kernel.org/show_bug.cgi?id=26562
+https://bugzilla.kernel.org/show_bug.cgi?id=26552
+May fix:
+https://bugs.freedesktop.org/show_bug.cgi?id=32556
+
+Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/atombios_crtc.c | 18 ++++++++++++++++--
+ drivers/gpu/drm/radeon/radeon_atombios.c | 10 ----------
+ drivers/gpu/drm/radeon/radeon_display.c | 3 +++
+ 3 files changed, 19 insertions(+), 12 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/atombios_crtc.c
++++ b/drivers/gpu/drm/radeon/atombios_crtc.c
+@@ -531,6 +531,7 @@ static u32 atombios_adjust_pll(struct dr
+ dp_clock = dig_connector->dp_clock;
+ }
+ }
++/* this might work properly with the new pll algo */
+ #if 0 /* doesn't work properly on some laptops */
+ /* use recommended ref_div for ss */
+ if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+@@ -548,6 +549,11 @@ static u32 atombios_adjust_pll(struct dr
+ adjusted_clock = mode->clock * 2;
+ if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
+ pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
++ /* rv515 needs more testing with this option */
++ if (rdev->family != CHIP_RV515) {
++ if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
++ pll->flags |= RADEON_PLL_IS_LCD;
++ }
+ } else {
+ if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
+ pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
+@@ -915,8 +921,16 @@ static void atombios_crtc_set_pll(struct
+ /* adjust pixel clock as needed */
+ adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
+
+- radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
+- &ref_div, &post_div);
++ /* rv515 seems happier with the old algo */
++ if (rdev->family == CHIP_RV515)
++ radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
++ &ref_div, &post_div);
++ else if (ASIC_IS_AVIVO(rdev))
++ radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
++ &ref_div, &post_div);
++ else
++ radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
++ &ref_div, &post_div);
+
+ atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
+
+--- a/drivers/gpu/drm/radeon/radeon_atombios.c
++++ b/drivers/gpu/drm/radeon/radeon_atombios.c
+@@ -1136,16 +1136,6 @@ bool radeon_atom_get_clock_info(struct d
+ p1pll->pll_out_min = 64800;
+ else
+ p1pll->pll_out_min = 20000;
+- } else if (p1pll->pll_out_min > 64800) {
+- /* Limiting the pll output range is a good thing generally as
+- * it limits the number of possible pll combinations for a given
+- * frequency presumably to the ones that work best on each card.
+- * However, certain duallink DVI monitors seem to like
+- * pll combinations that would be limited by this at least on
+- * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
+- * family.
+- */
+- p1pll->pll_out_min = 64800;
+ }
+
+ p1pll->pll_in_min =
+--- a/drivers/gpu/drm/radeon/radeon_display.c
++++ b/drivers/gpu/drm/radeon/radeon_display.c
+@@ -603,6 +603,9 @@ void radeon_compute_pll_legacy(struct ra
+ pll_out_max = pll->pll_out_max;
+ }
+
++ if (pll_out_min > 64800)
++ pll_out_min = 64800;
++
+ if (pll->flags & RADEON_PLL_USE_REF_DIV)
+ min_ref_div = max_ref_div = pll->reference_div;
+ else {
--- /dev/null
+From 18ff84da29b3f0c073e0ce6e341663cc6bcb0ab7 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher@gmail.com>
+Date: Wed, 2 Feb 2011 12:37:41 -0500
+Subject: drm/radeon/kms/evergreen: always set certain VGT regs at CP init
+
+From: Alex Deucher <alexdeucher@gmail.com>
+
+commit 18ff84da29b3f0c073e0ce6e341663cc6bcb0ab7 upstream.
+
+These should be handled by the clear_state setup, but set them
+directly as well just to be sure.
+
+Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/evergreen.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -1135,7 +1135,7 @@ static int evergreen_cp_start(struct rad
+ cp_me = 0xff;
+ WREG32(CP_ME_CNTL, cp_me);
+
+- r = radeon_ring_lock(rdev, evergreen_default_size + 15);
++ r = radeon_ring_lock(rdev, evergreen_default_size + 19);
+ if (r) {
+ DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
+ return r;
+@@ -1168,6 +1168,11 @@ static int evergreen_cp_start(struct rad
+ radeon_ring_write(rdev, 0xffffffff);
+ radeon_ring_write(rdev, 0xffffffff);
+
++ radeon_ring_write(rdev, 0xc0026900);
++ radeon_ring_write(rdev, 0x00000316);
++ radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
++ radeon_ring_write(rdev, 0x00000010); /* */
++
+ radeon_ring_unlock_commit(rdev);
+
+ return 0;
--- /dev/null
+From 87364760de5d631390c478fcbac8db1b926e0adf Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher@gmail.com>
+Date: Wed, 2 Feb 2011 19:46:06 -0500
+Subject: drm/radeon/kms: fix s/r issues with bios scratch regs
+
+From: Alex Deucher <alexdeucher@gmail.com>
+
+commit 87364760de5d631390c478fcbac8db1b926e0adf upstream.
+
+The accelerate mode bit gets checked by certain atom
+command tables to set up some register state. It needs
+to be clear when setting modes and set when not.
+
+Fixes:
+https://bugzilla.kernel.org/show_bug.cgi?id=26942
+
+Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/radeon_atombios.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_atombios.c
++++ b/drivers/gpu/drm/radeon/radeon_atombios.c
+@@ -2357,7 +2357,7 @@ void radeon_atom_initialize_bios_scratch
+ bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
+
+ /* tell the bios not to handle mode switching */
+- bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
++ bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
+
+ if (rdev->family >= CHIP_R600) {
+ WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
+@@ -2408,10 +2408,13 @@ void radeon_atom_output_lock(struct drm_
+ else
+ bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
+
+- if (lock)
++ if (lock) {
+ bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
+- else
++ bios_6_scratch &= ~ATOM_S6_ACC_MODE;
++ } else {
+ bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
++ bios_6_scratch |= ATOM_S6_ACC_MODE;
++ }
+
+ if (rdev->family >= CHIP_R600)
+ WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
--- /dev/null
+From be23da8ad219650517cbbb7acbeaeb235667113a Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher@gmail.com>
+Date: Tue, 18 Jan 2011 18:26:11 +0000
+Subject: drm/radeon/kms: make the mac rv630 quirk generic
+
+From: Alex Deucher <alexdeucher@gmail.com>
+
+commit be23da8ad219650517cbbb7acbeaeb235667113a upstream.
+
+Seems some other boards do this as well.
+
+Reported-by: Andrea Merello <andrea.merello@gmail.com>
+Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/radeon_atombios.c | 14 +++++---------
+ 1 file changed, 5 insertions(+), 9 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_atombios.c
++++ b/drivers/gpu/drm/radeon/radeon_atombios.c
+@@ -387,15 +387,11 @@ static bool radeon_atom_apply_quirks(str
+ *line_mux = 0x90;
+ }
+
+- /* mac rv630 */
+- if ((dev->pdev->device == 0x9588) &&
+- (dev->pdev->subsystem_vendor == 0x106b) &&
+- (dev->pdev->subsystem_device == 0x00a6)) {
+- if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
+- (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
+- *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
+- *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
+- }
++ /* mac rv630, rv730, others */
++ if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
++ (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
++ *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
++ *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
+ }
+
+ /* ASUS HD 3600 XT board lists the DVI port as HDMI */
--- /dev/null
+From 1e644d6dce366a7bae22484f60133b61ba322911 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher@gmail.com>
+Date: Thu, 27 Jan 2011 17:01:52 -0500
+Subject: drm/radeon/kms: re-emit full context state for evergreen blits
+
+From: Alex Deucher <alexdeucher@gmail.com>
+
+commit 1e644d6dce366a7bae22484f60133b61ba322911 upstream.
+
+clear state doesn't seem to work properly in some cases
+
+Fixes hangs in heavy 3D on some evergreen cards reported on
+IRC.
+
+May fix:
+https://bugs.freedesktop.org/show_bug.cgi?id=33381
+possibly others.
+
+Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/evergreen_blit_kms.c | 39 +++++++++++++++++++++++-----
+ 1 file changed, 33 insertions(+), 6 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
++++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+@@ -230,7 +230,7 @@ draw_auto(struct radeon_device *rdev)
+
+ }
+
+-/* emits 30 */
++/* emits 34 */
+ static void
+ set_default_state(struct radeon_device *rdev)
+ {
+@@ -243,6 +243,8 @@ set_default_state(struct radeon_device *
+ int num_hs_threads, num_ls_threads;
+ int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
+ int num_hs_stack_entries, num_ls_stack_entries;
++ u64 gpu_addr;
++ int dwords;
+
+ switch (rdev->family) {
+ case CHIP_CEDAR:
+@@ -409,6 +411,14 @@ set_default_state(struct radeon_device *
+ radeon_ring_write(rdev, 0x00000000);
+ radeon_ring_write(rdev, 0x00000000);
+
++ /* emit an IB pointing at default state */
++ dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
++ gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
++ radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
++ radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
++ radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
++ radeon_ring_write(rdev, dwords);
++
+ }
+
+ static inline uint32_t i2f(uint32_t input)
+@@ -439,8 +449,10 @@ static inline uint32_t i2f(uint32_t inpu
+ int evergreen_blit_init(struct radeon_device *rdev)
+ {
+ u32 obj_size;
+- int r;
++ int r, dwords;
+ void *ptr;
++ u32 packet2s[16];
++ int num_packet2s = 0;
+
+ /* pin copy shader into vram if already initialized */
+ if (rdev->r600_blit.shader_obj)
+@@ -448,8 +460,17 @@ int evergreen_blit_init(struct radeon_de
+
+ mutex_init(&rdev->r600_blit.mutex);
+ rdev->r600_blit.state_offset = 0;
+- rdev->r600_blit.state_len = 0;
+- obj_size = 0;
++
++ rdev->r600_blit.state_len = evergreen_default_size;
++
++ dwords = rdev->r600_blit.state_len;
++ while (dwords & 0xf) {
++ packet2s[num_packet2s++] = PACKET2(0);
++ dwords++;
++ }
++
++ obj_size = dwords * 4;
++ obj_size = ALIGN(obj_size, 256);
+
+ rdev->r600_blit.vs_offset = obj_size;
+ obj_size += evergreen_vs_size * 4;
+@@ -479,6 +500,12 @@ int evergreen_blit_init(struct radeon_de
+ return r;
+ }
+
++ memcpy_toio(ptr + rdev->r600_blit.state_offset,
++ evergreen_default_state, rdev->r600_blit.state_len * 4);
++
++ if (num_packet2s)
++ memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
++ packet2s, num_packet2s * 4);
+ memcpy(ptr + rdev->r600_blit.vs_offset, evergreen_vs, evergreen_vs_size * 4);
+ memcpy(ptr + rdev->r600_blit.ps_offset, evergreen_ps, evergreen_ps_size * 4);
+ radeon_bo_kunmap(rdev->r600_blit.shader_obj);
+@@ -564,7 +591,7 @@ int evergreen_blit_prepare_copy(struct r
+ /* calculate number of loops correctly */
+ ring_size = num_loops * dwords_per_loop;
+ /* set default + shaders */
+- ring_size += 46; /* shaders + def state */
++ ring_size += 50; /* shaders + def state */
+ ring_size += 10; /* fence emit for VB IB */
+ ring_size += 5; /* done copy */
+ ring_size += 10; /* fence emit for done copy */
+@@ -572,7 +599,7 @@ int evergreen_blit_prepare_copy(struct r
+ if (r)
+ return r;
+
+- set_default_state(rdev); /* 30 */
++ set_default_state(rdev); /* 34 */
+ set_shaders(rdev); /* 16 */
+ return 0;
+ }
--- /dev/null
+From a6f9761743bf35b052180f4a8bdae4d2cc0465f6 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon, 31 Jan 2011 16:48:50 -0500
+Subject: drm/radeon/kms: switch back to min->max pll post divider iteration
+
+From: Alex Deucher <alexdeucher@gmail.com>
+
+commit a6f9761743bf35b052180f4a8bdae4d2cc0465f6 upstream.
+
+Seems more reliable. Fixes:
+https://bugzilla.kernel.org/show_bug.cgi?id=26552
+
+Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/radeon_display.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_display.c
++++ b/drivers/gpu/drm/radeon/radeon_display.c
+@@ -517,7 +517,7 @@ void radeon_compute_pll(struct radeon_pl
+ max_fractional_feed_div = pll->max_frac_feedback_div;
+ }
+
+- for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
++ for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
+ uint32_t ref_div;
+
+ if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
--- /dev/null
+From 63a507800c8aca5a1891d598ae13f829346e8e39 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexdeucher@gmail.com>
+Date: Tue, 1 Feb 2011 19:06:46 -0500
+Subject: drm/radeon: remove 0x4243 pci id
+
+From: Alex Deucher <alexdeucher@gmail.com>
+
+commit 63a507800c8aca5a1891d598ae13f829346e8e39 upstream.
+
+0x4243 is a PCI bridge, not a GPU.
+
+Fixes:
+https://bugs.freedesktop.org/show_bug.cgi?id=33815
+
+Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ include/drm/drm_pciids.h | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/include/drm/drm_pciids.h
++++ b/include/drm/drm_pciids.h
+@@ -28,7 +28,6 @@
+ {0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
+ {0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \
+ {0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
+- {0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
+ {0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
+ {0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
+ {0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
--- /dev/null
+From 6bba2e116808ca12e30c8d88dfedabf8b8d67390 Mon Sep 17 00:00:00 2001
+From: Jerome Glisse <jglisse@redhat.com>
+Date: Wed, 26 Jan 2011 17:51:03 -0500
+Subject: radeon/kms: fix dp displayport mode validation
+
+From: Jerome Glisse <jglisse@redhat.com>
+
+commit 6bba2e116808ca12e30c8d88dfedabf8b8d67390 upstream.
+
+Check if there is a big enough dp clock & enough dp lane to
+drive the video mode provided.
+
+Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+Reviewed-By: Alex Deucher <alexdeucher@gmail.com>
+Signed-off-by: Dave Airlie <airlied@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/gpu/drm/radeon/atombios_dp.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/atombios_dp.c
++++ b/drivers/gpu/drm/radeon/atombios_dp.c
+@@ -187,9 +187,9 @@ static int dp_link_clock_for_mode_clock(
+ int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
+ {
+ int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock);
+- int bw = dp_lanes_for_mode_clock(dpcd, mode_clock);
++ int dp_clock = dp_link_clock_for_mode_clock(dpcd, mode_clock);
+
+- if ((lanes == 0) || (bw == 0))
++ if ((lanes == 0) || (dp_clock == 0))
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
dm-mpath-disable-blk_abort_queue.patch
arm-oprofile-fix-backtraces-in-timer-mode.patch
net-fec-fix-mmfr_op-type-in-fec_enet_mdio_write.patch
+drm-radeon-kms-add-quirk-for-mac-radeon-hd-2600-card.patch
+drm-radeon-kms-adjust-quirk-for-acer-laptop.patch
+drm-radeon-kms-make-the-mac-rv630-quirk-generic.patch
+radeon-kms-fix-dp-displayport-mode-validation.patch
+drm-radeon-kms-re-emit-full-context-state-for-evergreen-blits.patch
+drm-radeon-kms-switch-back-to-min-max-pll-post-divider-iteration.patch
+drm-radeon-kms-add-pll-debugging-output.patch
+drm-radeon-kms-add-new-pll-algo-for-avivo-asics.patch
+drm-radeon-kms-enable-new-pll-calculation-for-avivo-asics.patch
+drm-radeon-remove-0x4243-pci-id.patch
+drm-radeon-kms-evergreen-always-set-certain-vgt-regs-at-cp-init.patch
+drm-radeon-kms-fix-s-r-issues-with-bios-scratch-regs.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
