clk: spacemit: k3: Add PCIe DBI clock

Add PCIe DBI (Data Bus Interface) clock which was missing, This will
support PCIe driver to explicitly request and enable all clocks that
needed.

Link: https://patch.msgid.link/20260511-06-pci-clk-fix-v2-4-c9a5e563bab3@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>

diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c
index 8f0b743046ab75ff6ffcd258ff236fc463c31717..196d32194125c6bfda9974f360d41b8771f4d3f9 100644 (file)
--- a/drivers/clk/spacemit/ccu-k3.c
+++ b/drivers/clk/spacemit/ccu-k3.c
@@ -949,14 +949,19 @@ CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT
 
 CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0);
 CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0);
+CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(0), 0);
 CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0);
 CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0);
+CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(0), 0);
 CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0);
 CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0);
+CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(0), 0);
 CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0);
 CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0);
+CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(0), 0);
 CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0);
 CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0);
+CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(0), 0);
 
 static const struct clk_parent_data emac_1588_parents[] = {
        CCU_PARENT_NAME(vctcxo_24m),
@@ -1391,14 +1396,19 @@ static struct clk_hw *k3_ccu_apmu_hws[] = {
        [CLK_APMU_EDP1_PXCLK]           = &edp1_pxclk.common.hw,
        [CLK_APMU_PCIE_PORTA_MSTE]      = &pciea_mstr_clk.common.hw,
        [CLK_APMU_PCIE_PORTA_SLV]       = &pciea_slv_clk.common.hw,
+       [CLK_APMU_PCIE_PORTA_DBI]       = &pciea_dbi_clk.common.hw,
        [CLK_APMU_PCIE_PORTB_MSTE]      = &pcieb_mstr_clk.common.hw,
        [CLK_APMU_PCIE_PORTB_SLV]       = &pcieb_slv_clk.common.hw,
+       [CLK_APMU_PCIE_PORTB_DBI]       = &pcieb_dbi_clk.common.hw,
        [CLK_APMU_PCIE_PORTC_MSTE]      = &pciec_mstr_clk.common.hw,
        [CLK_APMU_PCIE_PORTC_SLV]       = &pciec_slv_clk.common.hw,
+       [CLK_APMU_PCIE_PORTC_DBI]       = &pciec_dbi_clk.common.hw,
        [CLK_APMU_PCIE_PORTD_MSTE]      = &pcied_mstr_clk.common.hw,
        [CLK_APMU_PCIE_PORTD_SLV]       = &pcied_slv_clk.common.hw,
+       [CLK_APMU_PCIE_PORTD_DBI]       = &pcied_dbi_clk.common.hw,
        [CLK_APMU_PCIE_PORTE_MSTE]      = &pciee_mstr_clk.common.hw,
        [CLK_APMU_PCIE_PORTE_SLV]       = &pciee_slv_clk.common.hw,
+       [CLK_APMU_PCIE_PORTE_DBI]       = &pciee_dbi_clk.common.hw,
        [CLK_APMU_EMAC0_BUS]            = &emac0_bus_clk.common.hw,
        [CLK_APMU_EMAC0_REF]            = &emac0_ref_clk.common.hw,
        [CLK_APMU_EMAC0_1588]           = &emac0_1588_clk.common.hw,