drm/amd/display: export get_power_profile interface for later use

[why]
export dcn401 get_power_profile for later asic.

Reviewed-by: Roman Li <roman.li@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index 60a0e7c95c735c2df5f83f257d92163c25b26f76..491860cc837874ce2ed71360aa9b024da47b2dff 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -1790,7 +1790,7 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
        }
 }
 
-static int dcn401_get_power_profile(const struct dc_state *context)
+int dcn401_get_power_profile(const struct dc_state *context)
 {
        int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;
        int dpm_level = 0;

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
index 5f3b0319cb5bb3d89840fbbaed67a06a2f8c2424..47f82b81826274f010f59f3cfafc0c43753fb17f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
@@ -32,6 +32,7 @@ void dcn401_get_default_tiling_info(struct dc_tiling_info *tiling_info);
 
 unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx);
 
+int dcn401_get_power_profile(const struct dc_state *context);
 /* Following are definitions for run time init of reg offsets */
 
 /* HUBP */

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
index 8175109a66b0f2094912e3f00d29ca2d624ff9d5..fa5d0558192cff26c1e3c28db9f0a19a1fb9a763 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
@@ -1791,6 +1791,7 @@ static struct resource_funcs dcn42_res_pool_funcs = {
        .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
        .prepare_mcache_programming = dcn42_prepare_mcache_programming,
        .build_pipe_pix_clk_params = dcn42_build_pipe_pix_clk_params,
+       .get_power_profile = dcn401_get_power_profile,
        .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe,
        .get_max_hw_cursor_size = dcn42_get_max_hw_cursor_size,
        .get_default_tiling_info = dcn10_get_default_tiling_info

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
index 8e7a09402de5cfa780c832681ff1dc19afe019ae..60acf0e423d97ea2bc41f3ebaccafef88094ec50 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h
@@ -586,5 +586,6 @@ enum dc_status dcn42_validate_bandwidth(struct dc *dc,
                                                          enum dc_validate_mode validate_mode);
 
 void dcn42_prepare_mcache_programming(struct dc *dc, struct dc_state *context);
+int dcn42_get_power_profile(const struct dc_state *context);
 
 #endif /* _DCN42_RESOURCE_H_ */