arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS

As per the S905X2 datasheet add missing cache information to the Amlogic
G12A SoC.

- Each Cortex-A53 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 512KB Unified L2 cache.

Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-4-linux.amoon@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index deee61dbe0741f52556fd89f8be18e4620d2ed85..1321ad95923d2c2bf0649214ddee30e14476a1ac 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -17,6 +17,12 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        #cooling-cells = <2>;
                };
@@ -26,6 +32,12 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        #cooling-cells = <2>;
                };
@@ -35,6 +47,12 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x2>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        #cooling-cells = <2>;
                };
@@ -44,6 +62,12 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x3>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
                        next-level-cache = <&l2>;
                        #cooling-cells = <2>;
                };
@@ -52,6 +76,9 @@
                        compatible = "cache";
                        cache-level = <2>;
                        cache-unified;
+                       cache-size = <0x80000>; /* L2. 512 KB */
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
                };
        };