arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC

Add the initial DTSI for the RZ/G3L SoC.
The files in this commit have the following meaning:
  - r9a08g046.dtsi:    RZ/G3L family SoC common parts
  - r9a08g046l48.dtsi: RZ/G3L R9A08G046L48 SoC-specific parts

Add placeholders to reuse the code for the Renesas SMARC II carrier
board.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260324114329.268249-9-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
new file mode 100644 (file)
index 0000000..28b0c75
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3L SoC
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+       compatible = "renesas,r9a08g046";
+       #address-cells = <2>;
+       #size-cells = <2>;
+       interrupt-parent = <&gic>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0>;
+                       device_type = "cpu";
+                       next-level-cache = <&L3_CA55>;
+                       enable-method = "psci";
+               };
+
+               cpu1: cpu@100 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0x100>;
+                       device_type = "cpu";
+                       next-level-cache = <&L3_CA55>;
+                       enable-method = "psci";
+               };
+
+               cpu2: cpu@200 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0x200>;
+                       device_type = "cpu";
+                       next-level-cache = <&L3_CA55>;
+                       enable-method = "psci";
+               };
+
+               cpu3: cpu@300 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0x300>;
+                       device_type = "cpu";
+                       next-level-cache = <&L3_CA55>;
+                       enable-method = "psci";
+               };
+
+               L3_CA55: cache-controller-0 {
+                       compatible = "cache";
+                       cache-unified;
+                       cache-size = <0x80000>;
+                       cache-level = <3>;
+               };
+       };
+
+       eth0_txc_tx_clk: eth0-txc-tx-clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       eth0_rxc_rx_clk: eth0-rxc-rx-clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       eth1_txc_tx_clk: eth1-txc-tx-clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       eth1_rxc_rx_clk: eth1-rxc-rx-clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       extal_clk: extal-clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board. */
+               clock-frequency = <0>;
+       };
+
+       psci {
+               compatible = "arm,psci-1.0", "arm,psci-0.2";
+               method = "smc";
+       };
+
+       soc: soc {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               scif0: serial@100ac000 {
+                       compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
+                       reg = <0 0x100ac000 0 0x400>;
+                       interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "eri", "rxi", "txi",
+                                         "bri", "dri", "tei";
+                       clocks = <&cpg CPG_MOD R9A08G046_SCIF0_CLK_PCK>;
+                       clock-names = "fck";
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A08G046_SCIF0_RST_SYSTEM_N>;
+                       status = "disabled";
+               };
+
+               i2c0: i2c@100ae000 {
+                       reg = <0 0x100ae000 0 0x400>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       /* placeholder */
+               };
+
+               canfd: can@100c0000 {
+                       reg = <0 0x100c0000 0 0x20000>;
+                       /* placeholder */
+               };
+
+               cpg: clock-controller@11010000 {
+                       compatible = "renesas,r9a08g046-cpg";
+                       reg = <0 0x11010000 0 0x10000>;
+                       clocks = <&extal_clk>,
+                                <&eth0_txc_tx_clk>, <&eth0_rxc_rx_clk>,
+                                <&eth1_txc_tx_clk>, <&eth1_rxc_rx_clk>;
+                       clock-names = "extal",
+                                     "eth0_txc_tx_clk", "eth0_rxc_rx_clk",
+                                     "eth1_txc_tx_clk", "eth1_rxc_rx_clk";
+                       #clock-cells = <2>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <0>;
+               };
+
+               sysc: system-controller@11020000 {
+                       compatible = "renesas,r9a08g046-sysc";
+                       reg = <0 0x11020000 0 0x10000>;
+                       interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "lpm_int", "ca55stbydone_int",
+                                         "cm33stbyr_int", "ca55_deny";
+               };
+
+               pinctrl: pinctrl@11030000 {
+                       reg = <0 0x11030000 0 0x10000>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       /* placeholder */
+               };
+
+               sdhi1: mmc@11c10000 {
+                       reg = <0x0 0x11c10000 0 0x10000>;
+                       /* placeholder */
+               };
+
+               pcie: pcie@11e40000 {
+                       reg = <0 0x11e40000 0 0x10000>;
+                       ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
+                       device_type = "pci";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       /* placeholder */
+
+                       pcie_port0: pcie@0,0 {
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               ranges;
+                               device_type = "pci";
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               /* placeholder */
+                       };
+               };
+
+               gic: interrupt-controller@12400000 {
+                       compatible = "arm,gic-v3";
+                       reg = <0x0 0x12400000 0 0x20000>,
+                             <0x0 0x12440000 0 0x80000>;
+                       #interrupt-cells = <3>;
+                       #address-cells = <0>;
+                       interrupt-controller;
+                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+               };
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+               interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
+       };
+};

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi
new file mode 100644 (file)
index 0000000..39b1141
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3L R9A08G046L48 SoC specific parts
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a08g046.dtsi"
+
+/ {
+       compatible = "renesas,r9a08g046l48", "renesas,r9a08g046";
+};