dt-bindings: clock: qcom,sm6115-dispcc: Define MDSS resets

Add the missing defines for MDSS resets, which are necessary to reset
the display subsystem in order to avoid issues caused by state left over
from the bootloader.

While here, align comment style with other SoCs.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Link: https://lore.kernel.org/r/20260303034847.13870-2-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/include/dt-bindings/clock/qcom,sm6115-dispcc.h b/include/dt-bindings/clock/qcom,sm6115-dispcc.h
index d1a6c45b50290313bf2bc03d593a2948ab5deded..ab8d312ade370e65efe1b9815d8b16691a3a6b6f 100644 (file)
--- a/include/dt-bindings/clock/qcom,sm6115-dispcc.h
+++ b/include/dt-bindings/clock/qcom,sm6115-dispcc.h
@@ -6,7 +6,7 @@
 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
 
-/* DISP_CC clocks */
+/* Clocks */
 #define DISP_CC_PLL0                   0
 #define DISP_CC_PLL0_OUT_MAIN          1
 #define DISP_CC_MDSS_AHB_CLK           2
@@ -30,7 +30,10 @@
 #define DISP_CC_SLEEP_CLK              20
 #define DISP_CC_SLEEP_CLK_SRC          21
 
-/* DISP_CC GDSCR */
+/* Resets */
+#define DISP_CC_MDSS_CORE_BCR                  0
+
+/* GDSCs */
 #define MDSS_GDSC                      0
 
 #endif