gcc/

	From Michael Frysinger  <michael.frysinger@analog.com>
	* config/bfin/bfin.c (bfin_cpus[]): Add 0.1 for bf522, bf523, bf524,
	bf525, bf526, bf527, bf542, bf544, bf547, bf548, and bf549.  Add 0.2
	for bf538.

gcc/testsuite/
	From Mike Frysinger  <michael.frysinger@analog.com>
	* gcc.target/bfin/mcpu-bf522.c: Check SILICON_REVISION is 0x0001.
	* gcc.target/bfin/mcpu-bf523.c: Likewise.
	* gcc.target/bfin/mcpu-bf524.c: Likewise.
	* gcc.target/bfin/mcpu-bf525.c: Likewise.
	* gcc.target/bfin/mcpu-bf526.c: Likewise.
	* gcc.target/bfin/mcpu-bf527.c: Likewise.
	* gcc.target/bfin/mcpu-bf542.c: Likewise.
	* gcc.target/bfin/mcpu-bf544.c: Likewise.
	* gcc.target/bfin/mcpu-bf547.c: Likewise.
	* gcc.target/bfin/mcpu-bf548.c: Likewise.
	* gcc.target/bfin/mcpu-bf549.c: Likewise.

From-SVN: r139935

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5f6fe227ec97e16f556bb0d7c98e5c84e17b6421..894a32d47959703516a651a5884c2c932406375c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2008-09-03  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+       From Michael Frysinger  <michael.frysinger@analog.com>
+       * config/bfin/bfin.c (bfin_cpus[]): Add 0.1 for bf522, bf523, bf524,
+       bf525, bf526, bf527, bf542, bf544, bf547, bf548, and bf549.  Add 0.2
+       for bf538.
+
 2008-09-03  Hari Sandanagobalane  <hariharan@picochip.com>
 
        Add picoChip port.

diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index bbd8223f34bf9f6de052ea0fa52a86dc2ba2fd09..86195eddaf060fa0a17da3f26db0df626b98f34c 100644 (file)
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -114,21 +114,33 @@ struct bfin_cpu
 
 struct bfin_cpu bfin_cpus[] =
 {
+  {"bf522", BFIN_CPU_BF522, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf522", BFIN_CPU_BF522, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf523", BFIN_CPU_BF523, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf523", BFIN_CPU_BF523, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf524", BFIN_CPU_BF524, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf524", BFIN_CPU_BF524, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf525", BFIN_CPU_BF525, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf525", BFIN_CPU_BF525, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf526", BFIN_CPU_BF526, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf526", BFIN_CPU_BF526, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf527", BFIN_CPU_BF527, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf527", BFIN_CPU_BF527, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
@@ -178,6 +190,8 @@ struct bfin_cpu bfin_cpus[] =
    WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf538", BFIN_CPU_BF538, 0x0003,
    WA_SPECULATIVE_LOADS | WA_RETS},
+  {"bf538", BFIN_CPU_BF538, 0x0002,
+   WA_SPECULATIVE_LOADS | WA_RETS},
 
   {"bf539", BFIN_CPU_BF539, 0x0004,
    WA_SPECULATIVE_LOADS | WA_RETS},
@@ -186,18 +200,28 @@ struct bfin_cpu bfin_cpus[] =
   {"bf539", BFIN_CPU_BF539, 0x0002,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf542", BFIN_CPU_BF542, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf542", BFIN_CPU_BF542, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf544", BFIN_CPU_BF544, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf544", BFIN_CPU_BF544, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf547", BFIN_CPU_BF547, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf547", BFIN_CPU_BF547, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf548", BFIN_CPU_BF548, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf548", BFIN_CPU_BF548, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 
+  {"bf549", BFIN_CPU_BF549, 0x0001,
+   WA_SPECULATIVE_LOADS | WA_RETS},
   {"bf549", BFIN_CPU_BF549, 0x0000,
    WA_SPECULATIVE_LOADS | WA_RETS},
 

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f76865e8ad3bba956c71d06795224e2d35ece25c..3cb12d1406f2e524acb47aa5eda26d012e6d0ff0 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,18 @@
+2008-09-03  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+       From Mike Frysinger  <michael.frysinger@analog.com>
+       * gcc.target/bfin/mcpu-bf522.c: Check SILICON_REVISION is 0x0001.
+       * gcc.target/bfin/mcpu-bf523.c: Likewise.
+       * gcc.target/bfin/mcpu-bf524.c: Likewise.
+       * gcc.target/bfin/mcpu-bf525.c: Likewise.
+       * gcc.target/bfin/mcpu-bf526.c: Likewise.
+       * gcc.target/bfin/mcpu-bf527.c: Likewise.
+       * gcc.target/bfin/mcpu-bf542.c: Likewise.
+       * gcc.target/bfin/mcpu-bf544.c: Likewise.
+       * gcc.target/bfin/mcpu-bf547.c: Likewise.
+       * gcc.target/bfin/mcpu-bf548.c: Likewise.
+       * gcc.target/bfin/mcpu-bf549.c: Likewise.
+
 2008-09-02  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 
        * gcc.c-torture/compile/pr33009.c: xfail on hppa*-*-*.

diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf522.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf522.c
index 205e37f3651ce49b06713c9ef125b64c3d8cfa77..7a1b3f491de4d6602e0967db4e5f037f21135368 100644 (file)
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf522.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf522.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED

diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf523.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf523.c
index eb21e6733e4989820bf2658fde0f2a673f616c92..46bc9c108251a9b384c27850a6e40c190433ff49 100644 (file)
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf523.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf523.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED

diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf524.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf524.c
index 7be635538896d4f484f0b9193f3f974a6d633fba..714be44de694f1f1bf691db4544c4c7ebb4eca50 100644 (file)
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf524.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf524.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED

diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf525.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf525.c
index 21dc2be96fb94001e46f29ea5888eff450905c41..0c1c60ccaf3a03cb69df6360d796fdeda9a2dd2e 100644 (file)
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf525.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf525.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED

diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf526.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf526.c
index bd1197e357b931ed89065c0c788c7dd0914da200..43d09e1a93d52a4e6664de734d1ea31a7b68618c 100644 (file)
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf526.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf526.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED

diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf527.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf527.c
index d419dd71cfa813018c6ae218460ed14fce5829a6..179d58714b71775a0aa3249de32affb8fb943c5b 100644 (file)
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf527.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf527.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF52x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED

diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c
index f36b16370b462ff024c55ef813dbc122a18c06d5..199936776dcfaa5d180f37807d469e4b5a83a503 100644 (file)
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED

diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c
index d1a0045d5035ba4bf40f8daf12debe8530772ec3..e23abe04e032a4fa9d80668bdcc4ca5d7f4c82fd 100644 (file)
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED

diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c
index cdf1995c920df1d57c7f96976d26b23c69646f52..fa34108520f6c1505cf64decb0a582d836cfc88e 100644 (file)
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED

diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c
index 2689eb2159641f4124c7de5c5ae35c36fcaf25ea..bc1bcd840d44436a1356db5d4b9d0225a9895b22 100644 (file)
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED

diff --git a/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c b/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c
index 01e068a3db8b4604f00e1fab27e1aff2e2acafca..d60ee3f51f0a9a37e937c7354e053a2521917b92 100644 (file)
--- a/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c
+++ b/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c
@@ -10,8 +10,8 @@
 #error "__ADSPBF54x__ is not defined"
 #endif
 
-#if __SILICON_REVISION__ != 0x0000
-#error "__SILICON_REVISION__ is not 0x0000"
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
 #endif
 
 #ifndef __WORKAROUNDS_ENABLED