drm/msm/a6xx: Enable IFPC on Adreno X1-85

Add the IFPC restore register list and enable IFPC support on Adreno
X1-85 gpu.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673384/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 4b3f18b2d2b95316f2d3612422f2a162d2cd9da1..7f495212c092f338b55d496e1b7645f8a5cfe0b7 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1353,6 +1353,69 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = {
 
 DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist);
 
+/* Applicable for X185, A750 */
+static const u32 a750_ifpc_reglist_regs[] = {
+       REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0,
+       REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
+       REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
+       REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
+       REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
+       REG_A6XX_TPL1_NC_MODE_CNTL,
+       REG_A6XX_SP_NC_MODE_CNTL,
+       REG_A6XX_CP_DBG_ECO_CNTL,
+       REG_A6XX_CP_PROTECT_CNTL,
+       REG_A6XX_CP_PROTECT(0),
+       REG_A6XX_CP_PROTECT(1),
+       REG_A6XX_CP_PROTECT(2),
+       REG_A6XX_CP_PROTECT(3),
+       REG_A6XX_CP_PROTECT(4),
+       REG_A6XX_CP_PROTECT(5),
+       REG_A6XX_CP_PROTECT(6),
+       REG_A6XX_CP_PROTECT(7),
+       REG_A6XX_CP_PROTECT(8),
+       REG_A6XX_CP_PROTECT(9),
+       REG_A6XX_CP_PROTECT(10),
+       REG_A6XX_CP_PROTECT(11),
+       REG_A6XX_CP_PROTECT(12),
+       REG_A6XX_CP_PROTECT(13),
+       REG_A6XX_CP_PROTECT(14),
+       REG_A6XX_CP_PROTECT(15),
+       REG_A6XX_CP_PROTECT(16),
+       REG_A6XX_CP_PROTECT(17),
+       REG_A6XX_CP_PROTECT(18),
+       REG_A6XX_CP_PROTECT(19),
+       REG_A6XX_CP_PROTECT(20),
+       REG_A6XX_CP_PROTECT(21),
+       REG_A6XX_CP_PROTECT(22),
+       REG_A6XX_CP_PROTECT(23),
+       REG_A6XX_CP_PROTECT(24),
+       REG_A6XX_CP_PROTECT(25),
+       REG_A6XX_CP_PROTECT(26),
+       REG_A6XX_CP_PROTECT(27),
+       REG_A6XX_CP_PROTECT(28),
+       REG_A6XX_CP_PROTECT(29),
+       REG_A6XX_CP_PROTECT(30),
+       REG_A6XX_CP_PROTECT(31),
+       REG_A6XX_CP_PROTECT(32),
+       REG_A6XX_CP_PROTECT(33),
+       REG_A6XX_CP_PROTECT(34),
+       REG_A6XX_CP_PROTECT(35),
+       REG_A6XX_CP_PROTECT(36),
+       REG_A6XX_CP_PROTECT(37),
+       REG_A6XX_CP_PROTECT(38),
+       REG_A6XX_CP_PROTECT(39),
+       REG_A6XX_CP_PROTECT(40),
+       REG_A6XX_CP_PROTECT(41),
+       REG_A6XX_CP_PROTECT(42),
+       REG_A6XX_CP_PROTECT(43),
+       REG_A6XX_CP_PROTECT(44),
+       REG_A6XX_CP_PROTECT(45),
+       REG_A6XX_CP_PROTECT(46),
+       REG_A6XX_CP_PROTECT(47),
+};
+
+DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist);
+
 static const struct adreno_info a7xx_gpus[] = {
        {
                .chip_ids = ADRENO_CHIP_IDS(0x07000200),
@@ -1442,12 +1505,14 @@ static const struct adreno_info a7xx_gpus[] = {
                .inactive_period = DRM_MSM_INACTIVE_PERIOD,
                .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
                          ADRENO_QUIRK_HAS_HW_APRIV |
-                         ADRENO_QUIRK_PREEMPTION,
+                         ADRENO_QUIRK_PREEMPTION |
+                         ADRENO_QUIRK_IFPC,
                .init = a6xx_gpu_init,
                .a6xx = &(const struct a6xx_info) {
                        .hwcg = a740_hwcg,
                        .protect = &a730_protect,
                        .pwrup_reglist = &a7xx_pwrup_reglist,
+                       .ifpc_reglist = &a750_ifpc_reglist,
                        .gmu_chipid = 0x7050001,
                        .gmu_cgc_mode = 0x00020202,
                        .bcms = (const struct a6xx_bcm[]) {
@@ -1487,6 +1552,7 @@ static const struct adreno_info a7xx_gpus[] = {
                .a6xx = &(const struct a6xx_info) {
                        .protect = &a730_protect,
                        .pwrup_reglist = &a7xx_pwrup_reglist,
+                       .ifpc_reglist = &a750_ifpc_reglist,
                        .gmu_chipid = 0x7090100,
                        .gmu_cgc_mode = 0x00020202,
                        .bcms = (const struct a6xx_bcm[]) {

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index cdb6d5f268b3b9c92b5356dc5b896e124cd26478..2f68394d6c3b05fcfedbdc88a43087f6190d2982 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -828,11 +828,10 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
        u32 *dest = (u32 *)&lock->regs[0];
        int i;
 
-       reglist = adreno_gpu->info->a6xx->pwrup_reglist;
-
        lock->gpu_req = lock->cpu_req = lock->turn = 0;
-       lock->ifpc_list_len = 0;
-       lock->preemption_list_len = reglist->count;
+
+       reglist = adreno_gpu->info->a6xx->ifpc_reglist;
+       lock->ifpc_list_len = reglist->count;
 
        /*
         * For each entry in each of the lists, write the offset and the current
@@ -843,6 +842,14 @@ static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
                *dest++ = gpu_read(gpu, reglist->regs[i]);
        }
 
+       reglist = adreno_gpu->info->a6xx->pwrup_reglist;
+       lock->preemption_list_len = reglist->count;
+
+       for (i = 0; i < reglist->count; i++) {
+               *dest++ = reglist->regs[i];
+               *dest++ = gpu_read(gpu, reglist->regs[i]);
+       }
+
        /*
         * The overall register list is composed of
         * 1. Static IFPC-only registers

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 124c63c4615930b00c64e488a498163ae35afccd..0b17d36c36a9567e6afa4269ae7783ed3578e40e 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -45,6 +45,7 @@ struct a6xx_info {
        const struct adreno_reglist *hwcg;
        const struct adreno_protect *protect;
        const struct adreno_reglist_list *pwrup_reglist;
+       const struct adreno_reglist_list *ifpc_reglist;
        u32 gmu_chipid;
        u32 gmu_cgc_mode;
        u32 prim_fifo_threshold;