5.15-stable patches

added patches:
	revert-drivers-clk-zynqmp-update-divider-round-rate-logic.patch

diff --git a/queue-5.15/revert-drivers-clk-zynqmp-update-divider-round-rate-logic.patch b/queue-5.15/revert-drivers-clk-zynqmp-update-divider-round-rate-logic.patch
new file mode 100644 (file)
index 0000000..6cc323a
--- /dev/null
+++ b/queue-5.15/revert-drivers-clk-zynqmp-update-divider-round-rate-logic.patch
@@ -0,0 +1,114 @@
+From stable+bounces-95417-greg=kroah.com@vger.kernel.org Mon Nov 25 17:10:26 2024
+From: jguittet.opensource@witekio.com
+Date: Mon, 25 Nov 2024 17:09:59 +0100
+Subject: Revert "drivers: clk: zynqmp: update divider round rate logic"
+To: stable@vger.kernel.org
+Cc: Joel Guittet <jguittet@witekio.com>, Joel Guittet <jguittet.opensource@witekio.com>
+Message-ID: <20241125160959.3522094-1-jguittet.opensource@witekio.com>
+
+From: Joel Guittet <jguittet@witekio.com>
+
+This reverts commit 9117fc44fd3a9538261e530ba5a022dfc9519620 which is
+commit 1fe15be1fb613534ecbac5f8c3f8744f757d237d upstream.
+
+It is reported to cause regressions in the 5.15.y tree, so revert it for
+now.
+
+Link: https://www.spinics.net/lists/kernel/msg5397998.html
+Signed-off-by: Joel Guittet <jguittet.opensource@witekio.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/clk/zynqmp/divider.c |   66 +++++++++++++++++++++++++++++++++++++++----
+ 1 file changed, 61 insertions(+), 5 deletions(-)
+
+--- a/drivers/clk/zynqmp/divider.c
++++ b/drivers/clk/zynqmp/divider.c
+@@ -110,6 +110,52 @@ static unsigned long zynqmp_clk_divider_
+       return DIV_ROUND_UP_ULL(parent_rate, value);
+ }
+ 
++static void zynqmp_get_divider2_val(struct clk_hw *hw,
++                                  unsigned long rate,
++                                  struct zynqmp_clk_divider *divider,
++                                  u32 *bestdiv)
++{
++      int div1;
++      int div2;
++      long error = LONG_MAX;
++      unsigned long div1_prate;
++      struct clk_hw *div1_parent_hw;
++      struct zynqmp_clk_divider *pdivider;
++      struct clk_hw *div2_parent_hw = clk_hw_get_parent(hw);
++
++      if (!div2_parent_hw)
++              return;
++
++      pdivider = to_zynqmp_clk_divider(div2_parent_hw);
++      if (!pdivider)
++              return;
++
++      div1_parent_hw = clk_hw_get_parent(div2_parent_hw);
++      if (!div1_parent_hw)
++              return;
++
++      div1_prate = clk_hw_get_rate(div1_parent_hw);
++      *bestdiv = 1;
++      for (div1 = 1; div1 <= pdivider->max_div;) {
++              for (div2 = 1; div2 <= divider->max_div;) {
++                      long new_error = ((div1_prate / div1) / div2) - rate;
++
++                      if (abs(new_error) < abs(error)) {
++                              *bestdiv = div2;
++                              error = new_error;
++                      }
++                      if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
++                              div2 = div2 << 1;
++                      else
++                              div2++;
++              }
++              if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO)
++                      div1 = div1 << 1;
++              else
++                      div1++;
++      }
++}
++
+ /**
+  * zynqmp_clk_divider_round_rate() - Round rate of divider clock
+  * @hw:                       handle between common and hardware-specific interfaces
+@@ -128,7 +174,6 @@ static long zynqmp_clk_divider_round_rat
+       u32 div_type = divider->div_type;
+       u32 bestdiv;
+       int ret;
+-      u8 width;
+ 
+       /* if read only, just return current value */
+       if (divider->flags & CLK_DIVIDER_READ_ONLY) {
+@@ -148,12 +193,23 @@ static long zynqmp_clk_divider_round_rat
+               return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
+       }
+ 
+-      width = fls(divider->max_div);
++      bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags);
++
++      /*
++       * In case of two divisors, compute best divider values and return
++       * divider2 value based on compute value. div1 will  be automatically
++       * set to optimum based on required total divider value.
++       */
++      if (div_type == TYPE_DIV2 &&
++          (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
++              zynqmp_get_divider2_val(hw, rate, divider, &bestdiv);
++      }
+ 
+-      rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags);
++      if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)
++              bestdiv = rate % *prate ? 1 : bestdiv;
+ 
+-      if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate))
+-              *prate = rate;
++      bestdiv = min_t(u32, bestdiv, divider->max_div);
++      *prate = rate * bestdiv;
+ 
+       return rate;
+ }

diff --git a/queue-5.15/series b/queue-5.15/series
index 00d89ce56b821370ae81ce9344a20adaede299b4..55eff6f6a6bc5b4e6eca2ceb5b017b204f030040 100644 (file)
--- a/queue-5.15/series
+++ b/queue-5.15/series
@@ -287,3 +287,4 @@ ksmbd-fix-slab-use-after-free-in-smb3_preauth_hash_rsp.patch
 xen-fix-the-issue-of-resource-not-being-properly-released-in-xenbus_dev_probe.patch
 alsa-usb-audio-fix-out-of-bounds-reads-when-finding-clock-sources.patch
 usb-ehci-spear-fix-call-balance-of-sehci-clk-handling-routines.patch
+revert-drivers-clk-zynqmp-update-divider-round-rate-logic.patch