block: systemace: Fix incorrect ace_write for width 16

Current implementation works fine for bus width = 16 bits because we
never get into "if" branch.

If one sets width to 8 bits there will be 2 consequent data accesses
write:
1. Correct data access for 8-bit bus
2. Unconditional (and in this case incorrect) data access as if data bus
is 16-bit wide

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c
index 247cf060e43ef4695cb4f5e81dd200ba0105c511..b1a3914cc38ca4a617907f81ee280b7314a53e3b 100644 (file)
--- a/drivers/block/systemace.c
+++ b/drivers/block/systemace.c
@@ -65,8 +65,8 @@ static void ace_writew(u16 val, unsigned off)
                writeb(val, base + off);
                writeb(val >> 8, base + off + 1);
 #endif
-       }
-       out16(base + off, val);
+       } else
+             out16(base + off, val);
 }
 
 static u16 ace_readw(unsigned off)