spi: zynq: Use divide by 8 baud rate for qspi dual stacked connection

Currently the qspi dual stacked support is available on afx boards,
there is a board hardware bug, that the controller will works on
divide by 8. hence changed the master mode baud rate divisor to /8
incase of dual stacked mode qspi.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

diff --git a/drivers/spi/zynq_qspips.c b/drivers/spi/zynq_qspips.c
index 057b289ed348ca181b09aa8c240bc19e7240912b..f185f97f079407d2c25aaaad375ebf7b9e0c3334 100644 (file)
--- a/drivers/spi/zynq_qspips.c
+++ b/drivers/spi/zynq_qspips.c
@@ -265,6 +265,8 @@ static void xqspips_init_hw(int is_dual, unsigned int cs)
        config_reg = readl(&xqspips_base->confr);
        config_reg &= 0xFBFFFFFF; /* Set little endian mode of TX FIFO */
        config_reg |= 0x8000FCC1;
+       if (is_dual == MODE_DUAL_STACKED)
+               config_reg |= 0x10;
        writel(config_reg, &xqspips_base->confr);
 
        if (is_dual == MODE_DUAL_PARALLEL)