]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
pinctrl: airoha: an7583: fix misprint in gpio19 pinconf
authorMikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Sat, 6 Jun 2026 02:03:35 +0000 (05:03 +0300)
committerLinus Walleij <linusw@kernel.org>
Thu, 11 Jun 2026 11:52:47 +0000 (13:52 +0200)
Pin 21 (gpio19) duplicate pinconf settings of pin 20. Fix it using
a proper bit number in the configuration register.

Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
drivers/pinctrl/airoha/pinctrl-airoha.c

index 0725a7ece25d98db70ed675d05fdbb2410cea7e5..a966144bad214543cc438b1cd6efc0d52284ff8e 100644 (file)
@@ -1851,7 +1851,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
        PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
        PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
        PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
-       PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(18)),
+       PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
        PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
        PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
        PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
@@ -1968,7 +1968,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
        PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
        PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
        PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
-       PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(18)),
+       PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
        PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
        PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
        PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
@@ -2085,7 +2085,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
        PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
        PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
        PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
-       PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(18)),
+       PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
        PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
        PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
        PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
@@ -2202,7 +2202,7 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
        PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
        PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
        PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
-       PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(18)),
+       PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
        PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
        PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
        PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),