arm64: dts: qcom: x1e80100: Add videocc

Add the video clock controller for X1E80100, similar to sm8550.dtsi. It
provides the needed clocks/power domains for the iris video codec.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-6-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 4dba9f2b64f7620e880f358b4b69efb3ad50d151..f293b13ecc0ce426661187ac793f147d12434fcb 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
+#include <dt-bindings/clock/qcom,sm8450-videocc.h>
 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
@@ -5182,6 +5183,20 @@
                        };
                };
 
+               videocc: clock-controller@aaf0000 {
+                       compatible = "qcom,x1e80100-videocc";
+                       reg = <0 0x0aaf0000 0 0x10000>;
+                       clocks = <&bi_tcxo_div2>,
+                                <&gcc GCC_VIDEO_AHB_CLK>;
+                       power-domains = <&rpmhpd RPMHPD_MMCX>,
+                                       <&rpmhpd RPMHPD_MXC>;
+                       required-opps = <&rpmhpd_opp_low_svs>,
+                                       <&rpmhpd_opp_low_svs>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                mdss: display-subsystem@ae00000 {
                        compatible = "qcom,x1e80100-mdss";
                        reg = <0 0x0ae00000 0 0x1000>;