Fixes for 5.10

Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/queue-5.10/pwm-tegra-fix-32-bit-build.patch b/queue-5.10/pwm-tegra-fix-32-bit-build.patch
new file mode 100644 (file)
index 0000000..669798b
--- /dev/null
+++ b/queue-5.10/pwm-tegra-fix-32-bit-build.patch
@@ -0,0 +1,47 @@
+From 9f841b8cc055ddc41b6eefc597e6a61b8145f59a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 10 Nov 2022 11:45:48 +0000
+Subject: pwm: tegra: Fix 32 bit build
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Steven Price <steven.price@arm.com>
+
+[ Upstream commit dd1f1da4ada5d8ac774c2ebe97230637820b3323 ]
+
+The value of NSEC_PER_SEC << PWM_DUTY_WIDTH doesn't fix within a 32 bit
+integer causing a build warning/error (and the value truncated):
+
+  drivers/pwm/pwm-tegra.c: In function ‘tegra_pwm_config’:
+  drivers/pwm/pwm-tegra.c:148:53: error: result of ‘1000000000 << 8’ requires 39 bits to represent, but ‘long int’ only has 32 bits [-Werror=shift-overflow=]
+    148 |   required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
+        |                                                     ^~
+
+Explicitly cast to a u64 to ensure the correct result.
+
+Fixes: cfcb68817fb3 ("pwm: tegra: Improve required rate calculation")
+Signed-off-by: Steven Price <steven.price@arm.com>
+Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pwm/pwm-tegra.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
+index 36cc1452cb7a..f3528c56e894 100644
+--- a/drivers/pwm/pwm-tegra.c
++++ b/drivers/pwm/pwm-tegra.c
+@@ -142,7 +142,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+                * source clock rate as required_clk_rate, PWM controller will
+                * be able to configure the requested period.
+                */
+-              required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
++              required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
+                                                    period_ns);
+ 
+               err = clk_set_rate(pc->clk, required_clk_rate);
+-- 
+2.35.1
+

diff --git a/queue-5.10/series b/queue-5.10/series
index 3aaa9600d127926fee423083cc0bf1638c3429fb..8ccf7fe96d0b5d1071c4a8be1d3a230e05955a85 100644 (file)
--- a/queue-5.10/series
+++ b/queue-5.10/series
@@ -572,3 +572,4 @@ gcov-add-support-for-checksum-field.patch
 ovl-fix-use-inode-directly-in-rcu-walk-mode.patch
 media-dvbdev-fix-build-warning-due-to-comments.patch
 media-dvbdev-fix-refcnt-bug.patch
+pwm-tegra-fix-32-bit-build.patch